Nonvolatile storage element

ABSTRACT

The object of the present invention is to provide a nonvolatile storage element capable of suppressing retention degradation. 
     A nonvolatile storage element is provided with a semiconductor substrate and a floating gate provided above the semiconductor substrate, in which the floating gate has an area of 30 μm 2  or more.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a nonvolatile storage element.

Description of the Related Art

By the use of a nonvolatile storage element in which a threshold voltageVth is adjustable in a metal-oxide-semiconductor field effect transistor(MOSFET) configuring an analog circuit, variations in electriccharacteristics or temperature dependency can be controlled in somecases. For example, PTL 1 has proposed a method for eliminatingmanufacturing variations in a reference voltage generation circuit bythe use of a nonvolatile storage element for an enhancement MOSFET and adepression MOSFET configuring the reference voltage generation circuit.

The nonvolatile storage element achieving such a circuit has a structureprovided with a tunnel insulating film, a floating gate, and a controlgate. The nonvolatile storage element has a structure referred to as aFLOTOX (Floating Gate Tunneling Oxide) type in which a charge isinjected or a charge is extracted by FN (Fowler-Nordheim) tunnelingthrough the tunnel insulating film.

FIGS. 32A and 32B are figures schematically illustrating an example ofthe structure of a FLOTOX nonvolatile storage element FM in the use fora conventional memory cell array. FIG. 32A is a plan view of thenonvolatile storage element FM. FIG. 32B is a cross-sectional view ofthe nonvolatile storage element FM cut along the Z-Z line illustrated inFIG. 32A.

As illustrated in FIGS. 32A and 32B, the nonvolatile storage element FMis provided with a semiconductor substrate SB, a gate oxide film GIformed on the semiconductor substrate SB, and a floating gate FG formedon the gate oxide film GI. Moreover, the nonvolatile storage element FMis provided with an insulating film IF formed on the floating gate FGand a control gate CG formed on the insulating film IF. Moreover, thenonvolatile storage element FM is provided with a source diffusion layerSD and a drain diffusion layer DD formed in the semiconductor substrateSB. Apart of the drain diffusion layer DD is disposed below the floatinggate FG. Between the floating gate FG and the drain diffusion layer DD,a tunnel oxide film TO is formed.

A voltage is applied to the control gate CG or the drain diffusion layerDD and a charge is injected into the floating gate FG or extracted fromthe floating gate FG by the FN tunneling through the tunnel oxide filmTO. Thus, the nonvolatile storage element FM can control the thresholdvoltage Vth at which an inversion layer is formed on the semiconductorsubstrate SB when a voltage is applied to the control gate CG. In thememory cell, a case where a predetermined read voltage is applied to thecontrol gate CG and the threshold voltage Vth exceeds the read voltage(case where the MOSFET is not changed from an OFF state to an ON state)is set to “0”. On the other hand, in the memory cell, a case where apredetermined read voltage is applied to the control gate CG and thethreshold voltage Vth is less than the read voltage (case where theMOSFET is changed from the OFF state to the ON state) is set to “1”.Thus, information can be stored in the memory cell. The memory cellarray provided with two or more of such memory cells is laid out in adesign rule close to the minimum in a manufacturing process because ahigh integration is demanded. In the case of the minimum dimension ruleof 0.5 μm, the tunnel oxide film TO has a dimension of 0.5 μm×0.5 μm,the floating gate FG has a dimension of 2.6 μm×2.4 μm, and the arearatio of the tunnel oxide film TO to the floating gate FG is 0.04 as anexample.

CITATION LIST Patent Literature

PTL 1: JP 2015-011454 A

SUMMARY OF THE INVENTION

However, when the FLOTOX nonvolatile storage element is used as theMOSFET in an analog circuit, a fluctuation in the threshold voltage Vthdirectly affects circuit characteristics as compared with a case ofbeing used as a usual memory cell. Therefore, when used in the analogcircuit, the allowance of the nonvolatile storage element to thefluctuation in the threshold voltage Vth due to charge leakage from thefloating gate (retention degradation) becomes very small as comparedwith the case of being used in the memory cell.

Moreover, the FLOTOX nonvolatile storage element needs to take the areaof the floating gate larger than that in the case of the memory cellarray, e.g., 30 μm² or more, in order to obtain a desired current indriving. In this case, the amount of charges to be injected into thefloating gate FG increases, and therefore damage on the tunnel oxidefilm in writing increases. Thus, the FLOTOX nonvolatile storage elementhas a problem that the fluctuation in the threshold voltage Vth due tocharge leakage from the floating gate through a defect generated in thetunnel oxide film (hereinafter sometimes referred to as “first moderetention degradation”) is likely to occur.

As a method for solving the problem, it is considered to increase thearea of the tunnel oxide film and reduce the amount of charges passingthrough the tunnel oxide film per unit area thereof to thereby reducethe damage on the tunnel oxide film. However, the FLOTOX nonvolatilestorage element has a problem that, when the area of the tunnel oxidefilm is increased, the occurrence probability of the fluctuation in thethreshold voltage Vth due to the fact that the a charge in the floatinggate excited by thermal energy jumps over the energy barrier of thetunnel oxide film and leaks (hereinafter sometimes referred to as“second mode retention degradation) becomes high.

It is an object of the present invention to provide a nonvolatilestorage element capable of suppressing the retention degradation.

A nonvolatile storage element according to one aspect of the presentinvention is provided with a semiconductor substrate, a floating gateprovided above the semiconductor substrate, a control gate disposedabove the floating gate to be insulated from the floating gate, a firstregion provided in the semiconductor substrate and partially disposedbelow the floating gate, and a tunnel insulating film at least partiallydisposed between the floating gate and the first region and having anarea ratio to the floating gate of 0.002 or more and 1 or less.

According to one aspect of the present invention, the retentiondegradation can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a principal portion illustrating the schematicconfiguration of a nonvolatile storage element M1 according to a firstembodiment of the present invention.

FIGS. 2A to 2C are figures illustrating the schematic configuration ofthe nonvolatile storage element M1 according to the first embodiment ofthe present invention, in which FIG. 2A is a cross-sectional view of thenonvolatile storage element M1 cut along the A-A line illustrated inFIG. 1, FIG. 2B is a cross-sectional view of the nonvolatile storageelement M1 cut along the B1-B1 line (B2-B2 line) illustrated in FIG. 1,and FIG. 2C is a cross-sectional view of the nonvolatile storage elementM1 cut along the C-C line illustrated in FIG. 1.

FIGS. 3A and 3B are figures explaining first mode retention degradationof the nonvolatile storage element M1 according to the first embodimentof the present invention, in which FIG. 3A is a graph illustrating thearea ratio of a tunnel insulating film to a floating gate when the ratioof samples having a threshold voltage fluctuation of less than 100 mV is99.87% or more and FIG. 3B is a graph illustrating the area ratio of thetunnel insulating film to the floating gate when the ratio of sampleshaving a threshold voltage fluctuation of less than 100 mV is 99.997% ormore.

FIGS. 4A and 4B are figures explaining second mode retention degradationof the nonvolatile storage element M1 according to the first embodimentof the present invention, in which FIG. 4A is a graph illustrating thearea of the tunnel insulating film when the ratio of samples having athreshold voltage fluctuation of less than 100 mV is 99.87% or more andFIG. 4B is a graph illustrating the area of the tunnel insulating filmwhen the ratio of samples having a threshold voltage fluctuation of lessthan 100 mV is 99.997% or more.

FIGS. 5A and 5B are figures explaining an adaptive region of the areaconfiguration of the floating gate and the tunnel insulating film of thenonvolatile storage element M1 according to the first embodiment of thepresent invention, in which FIG. 5A is a figure illustrating theadaptive region of the area configuration in which it is expected that99.87% of the nonvolatile storage elements M1 can secure the life timeof ten years or more and FIG. 5B is a figure illustrating the adaptiveregion of the area configuration in which it is expected that 99.997% ofthe nonvolatile storage elements M1 can secure the life time of tenyears or more.

FIG. 6 is a figure explaining a specific region PA of a driving elementMv1 provided in the nonvolatile storage element M1 according to thefirst embodiment and is a figure illustrating an example of temperaturecharacteristic of a drain current.

FIG. 7 is a figure explaining the specific region PA of the drivingelement Mv1 provided in the nonvolatile storage element M1 according tothe first embodiment and is a figure illustrating an example of therelationship between the gate width and a temperature independentcurrent of the driving element Mv1.

FIG. 8 is a figure explaining the specific region PA of the drivingelement Mv1 provided in the nonvolatile storage element M1 according tothe first embodiment and is a figure illustrating an example of therelationship between the gate length and the temperature independentcurrent of the driving element Mv1.

FIGS. 9A to 9F are cross-sectional views of a manufacturing process(No. 1) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 10A to 10F are cross-sectional views of the manufacturing process(No. 2) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 11A to 11F are cross-sectional views of the manufacturing process(No. 3) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 12A to 12C are cross-sectional views of the manufacturing process(No. 4) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 13A to 13F are cross-sectional views of the manufacturing process(No. 5) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 14A to 14F are cross-sectional views of the manufacturing process(No. 6) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 15A to 15F are cross-sectional views of the manufacturing process(No. 7) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 16A to 16F are cross-sectional views of the manufacturing process(No. 8) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 17A to 17F are cross-sectional views of the manufacturing process(No. 9) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIGS. 18A to 18C are cross-sectional views of the manufacturing process(No. 10) of the nonvolatile storage element M1 according to the firstembodiment of the present invention.

FIG. 19 is a circuit configuration diagram of a reference voltagegeneration circuit RC3 provided with the nonvolatile storage elementaccording to the first embodiment of the present invention.

FIG. 20 is a figure for explaining the reference voltage generationcircuit RC3 provided with the nonvolatile storage element according tothe first embodiment of the present invention and for explaining a stateof adjusting a nonvolatile storage element M31 on the upper stage sideof the reference voltage generation circuit RC3 to a depression state.

FIG. 21 is a figure for explaining the reference voltage generationcircuit RC3 provided with the nonvolatile storage element according tothe first embodiment of the present invention and for explaining a stateof adjusting a nonvolatile storage element M33 on the lower stage sideof the reference voltage generation circuit RC3 to an enhancement state.

FIG. 22 is a figure illustrating an example of current/voltagecharacteristics of a depression transistor Md and an enhancementtransistor Me.

FIGS. 23A to 23C are figures illustrating the schematic configuration ofa nonvolatile storage element M2 according to a second embodiment of thepresent invention, in which FIG. 23A is a plan view of a principalportion of the nonvolatile storage element M2, FIG. 23B is across-sectional view of the nonvolatile storage element M2 cut along theD-D line illustrated in FIG. 23A, and FIG. 23C is a cross-sectional viewof the nonvolatile storage element M2 cut along the E-E line illustratedin FIG. 23A.

FIG. 24 is a circuit configuration diagram for explaining a referencevoltage generation circuit RC2 provided with the nonvolatile storageelement according to the second embodiment of the present invention.

FIG. 25 is a circuit configuration diagram for explaining the referencevoltage generation circuit RC2 provided with the nonvolatile storageelement according to the second embodiment of the present invention andfor explaining a state of adjusting a nonvolatile storage element M21 onthe upper stage side of the reference voltage generation circuit RC2 toa depression state.

FIG. 26 is a circuit configuration diagram for explaining the referencevoltage generation circuit RC2 provided with the nonvolatile storageelement according to the second embodiment of the present invention andfor explaining a state of adjusting a nonvolatile storage element M22 onthe lower stage side of the reference voltage generation circuit RC2 toan enhancement state.

FIGS. 27A and 27B are figures illustrating the schematic configurationof a nonvolatile storage element M7 according to a third embodiment ofthe present invention, in which FIG. 27A is a plan view of a principalportion of the nonvolatile storage element M7 and FIG. 27B is across-sectional view of the nonvolatile storage element M7 cut along theF-F line illustrated in FIG. 27A.

FIG. 28 is a circuit configuration diagram for explaining a referencevoltage generation circuit RC6 provided with the nonvolatile storageelement according to the third embodiment of the present invention.

FIG. 29 is a circuit configuration diagram for explaining a referencevoltage generation circuit RC7 provided with the nonvolatile storageelement according to the third embodiment of the present invention.

FIG. 30 is a circuit configuration diagram for explaining a referencevoltage generation circuit RC7 provided with the nonvolatile storageelement according to the third embodiment of the present invention andfor explaining a state of adjusting a nonvolatile storage element M71 onthe upper stage side of the reference voltage generation circuit RC7 toa depression state.

FIG. 31 is a circuit configuration diagram for explaining the referencevoltage generation circuit RC7 provided with the nonvolatile storageelement according to the third embodiment of the present invention andfor explaining a state of adjusting a nonvolatile storage element M72 onthe lower stage side of the reference voltage generation circuit RC7 toan enhancement state.

FIGS. 32A and 32B are figures illustrating the schematic configurationof a conventional nonvolatile storage element FM, in which FIG. 32A is afigure schematically illustrating the plane of the nonvolatile storageelement FM and FIG. 32B is a figure schematically illustrating the crosssection of nonvolatile storage element FM cut along the Z-Z lineillustrated in FIG. 32A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Next, nonvolatile storage elements according to embodiments of thepresent invention are described with reference to the drawings.

Hereinafter, a description is given taking type nonvolatile storageelement of an N-type MOSFET FLOTOX as an example of the nonvolatilestorage elements according to the embodiments. However, the nonvolatilestorage element is not limited to this structure and is not limited tothe N-type insofar as the nonvolatile storage element is an activeelement (transistor) having a charge retention region.

First Embodiment

A nonvolatile storage element according to a first embodiment of thepresent invention is described with reference to FIGS. 1 to 22. First,the schematic configuration of the nonvolatile storage element M1according to this embodiment is described with reference to FIGS. 1 and2A to 2C. A driving element Mv1 and a dummy element Mm1 (details thereofare described later) provided in the nonvolatile storage element M1 havethe same structure. Therefore, FIG. 2B illustrates both the referencenumerals of constituent components of the dummy element Mm1 and thedriving element Mv1, in which round brackets are given to theconstituent components of the dummy element Mm1 and round brackets arenot given to the constituent components of the driving element Mv1. Whenthe same reference numeral is used for the constituent component of eachof the driving element Mv1 and the dummy element Mm1, only the referencenumeral having no round brackets is given to the constituent component.

As illustrated in FIG. 1, the nonvolatile storage element M1 accordingto this embodiment is provided with a writing element Mw1, the drivingelement (an example of a driving MOSFET) Mv1 disposed next to thewriting element Mw1, and the dummy element Mm1 disposed next to thedriving element Mv1. The nonvolatile storage element M1 is provided witha floating gate FG1 and a control gate CG1 shared by the writing elementMw1, the driving element Mv1, and the dummy element Mm1. Although thedetails are described later, the nonvolatile storage element M1 isconfigured so that a charge can be injected into the floating gate FG1or a charge can be emitted from the floating gate FG1 through a chargeinlet 14 provided in the writing element Mw1 by applying a predeterminedvoltage to a first impurity diffusion region IAa and the control gateCG1 disposed below the floating gate FG1. This makes it possible for thenonvolatile storage element M1 to change a threshold voltage and holdthe changed threshold voltage to control variations of electriccharacteristics or temperature dependency.

The nonvolatile storage element M1 is element-isolated by an elementisolation region 41 (see FIGS. 2A to 2C) formed in a P-typesemiconductor substrate 9A (see FIGS. 2A to 2C), for example, fromanother nonvolatile storage element (not illustrated) formed on the samesemiconductor substrate 9A.

As illustrated in FIG. 2A, the writing element Mw1 provided in thenonvolatile storage element M1 is provided with the semiconductorsubstrate 9A and a gate insulating film 16 w provided on thesemiconductor substrate 9A. In the semiconductor substrate 9A, a P-typewell (hereinafter abbreviated as “P-well”) region 10A is formed. Thegate insulating film 16 w is made of silicon dioxide (SiO₂) and isdisposed on the P-well region 10A. The gate insulating film 16 w may bemade of silicon nitride (SiN) without being limited to the silicondioxide.

The writing element Mw1 is provided with the floating gate FG1 providedabove the semiconductor substrate 9A. A part of the floating gate FG1 isdisposed on the gate insulating film 16 w. The floating gate FG1 is madeof polysilicon.

The writing element Mw1 is provided with the control gate CG1 which isdisposed above the floating gate FG1 to be insulated from the floatinggate FG1. The control gate CG1 is made of polysilicon, for example.

The writing element Mw1 is provided with the first impurity diffusionregion (an example of the first region) IAa provided in thesemiconductor substrate 9A and partially disposed below the floatinggate FG1 and a second impurity diffusion region IAb provided in thesemiconductor substrate 9A. The first impurity diffusion region IAa andthe second impurity diffusion region IAb are provided in the P-wellregion 10A.

As illustrated in FIG. 1, the second impurity diffusion region IAb isformed in a part of the side (one of both sides) of the floating gateFG1 in a plan view of the nonvolatile storage element M1. Herein, theplan view refers to a state where the plane (element formation surface)of the semiconductor substrate 9A on which the floating gate FG1, thecontrol gate CG1, and the like are formed is viewed in an orthogonaldirection to element formation surface. As illustrated in FIGS. 1 and2A, the second impurity diffusion region IAb has an N-type lowconcentration impurity drain (Lightly Doped Drain, hereinafterabbreviated as “LDD”) layer 12 b and a contact layer 13 b having animpurity concentration higher than that of the LDD layer 12 b. Thecontact layer 13 b is provided in the LDD layer 12 b. The contact layer13 b is provided in order to take an ohmic contact between the secondimpurity diffusion region IAb and a plug 51 b (see FIG. 2A, details aredescribed later).

As illustrated in FIGS. 1 and 2A, the first impurity diffusion regionIAa has a diffusion layer 11 a disposed in a part below the floatinggate FG1, an N-type LDD layer 12 a disposed adjacent to the diffusionlayer 11 a, and a contact layer 13 a having an impurity concentrationhigher than that of the LDD layer 12 a.

As illustrated in FIGS. 1 and 2A, the contact layer 13 a is provided inthe LDD layer 12 a. The contact layer 13 a is provided in order to takean ohmic contact between the first impurity diffusion region IAa and aplug 51 a (see FIG. 2A, details are described later). As illustrated inFIG. 1, the first impurity diffusion region IAa is formed over a partbelow the floating gate FG1 and a part of the side (the other side ofboth sides) of the floating gate FG1 in the plan view of the nonvolatilestorage element M1. The diffusion layer 11 a is provided in a part belowthe floating gate FG1 and the LDD layer 12 a and the contact layer 13 aare provided in a part of the side of the floating gate FG1. The LDDlayer 12 a and the LDD layer 12 b are provided with the floating gateFG1 interposed therebetween in the plan view of the nonvolatile storageelement M1.

As illustrated in FIGS. 1 and 2A, the writing element Mw1 is providedwith a tunnel insulating film 15 at least partially disposed between thefloating gate FG1 and the first impurity diffusion region IAa and havingan area ratio to the floating gate FG1 of 0.002 or more and 1 or less.In this embodiment, the entire tunnel insulating film 15 is disposedbetween the floating gate FG1 and the diffusion layer 11 a. Asillustrated in FIG. 1, the tunnel insulating film 15 is formed to besmaller than the entire floating gate FG1 in the plan view of thenonvolatile storage element M1. The entire floating gate FG1 has an areaof 30 μm² or more in the plan view of the nonvolatile storage elementM1. The area of the tunnel insulating film 15 is 0.06 μm² or more and 54μm² or less in the plan view of the nonvolatile storage element M1. Whenthe area of the entire floating gate FG1 is 30 μm² of the minimum valueand the area ratio of the tunnel insulating film 15 to the floating gateFG1 is 0.002 of the minimum value, the area of the tunnel insulatingfilm 15 is 0.06 μm² of the minimum value. Herein, the “entire floatinggate FG1” means the floating gate provided in one nonvolatile storageelement M1 and does not mean the floating gate in predeterminedportions, such as a portion where the writing element Mw1 is provided, aportion where the driving element Mv1 is provided, and a portion wherethe dummy element Mm1 is provided. Therefore, the “entire floating gateFG1” is distinguished from a “specific region PA of the floating FG1”(details are described later) in the portion where the driving elementMv1 is provided. Hereinafter, the “floating gate FG1” means the “entirefloating gate FG1” unless otherwise specified as the “specific region PAof the floating gate FG1”. The area of the tunnel insulating film 15 inthis embodiment is 25 μm², for example. Therefore, in this embodiment,the ratio of the area of the tunnel insulating film 15 to the area ofthe floating gate FG1 (area ratio), i.e., a value determined by dividingthe area of the tunnel insulating film 15 by the area of the floatinggate FG1, is 0.017. Although the details are described later, first moderetention degradation can be improved when the area ratio of the tunnelinsulating film 15 to the floating gate FG1 is 0.002 or more.

In order to perform writing of injecting a charge into the floating gateFG1 or extracting a charge from the floating gate FG1 by FN tunneling,the thickness of the tunnel insulating film 15 may be 7 nm or more and12 nm or less. In this embodiment, the film thickness of the tunnelinsulating film 15 is 9.8 nm, for example. When the film thickness ofthe tunnel insulating film 15 is 7 to 12 nm, direct tunneling of acharge becomes more unlikely to occur and a charge is more easilyretained in the floating gate FG1 as compared with the case where thefilm thickness is less than 7 nm. On the other hand, when the filmthickness of the tunnel insulating film 15 is 7 to 12 nm, the injectionof a charge into the floating gate FG1 and the extraction of a chargefrom the floating gate FG1 can be accelerated as compared with the casewhere the film thickness is larger than 12 nm. The tunnel insulatingfilm 15 may be formed to have a film thickness smaller than that of thegate insulating film 16 w. A region of the floating gate FG1corresponding to the tunnel insulating film 15 serves as the chargeinlet 14 injecting a charge into the floating gate FG1 or emitting acharge from the floating gate FG1. More specifically, the floating gateFG1 has the charge inlet 14 for injecting a charge or emitting a chargeand functions as a charge retention region.

As illustrated in FIG. 2B, the driving element Mv1 provided in thenonvolatile storage element M1 is provided with the semiconductorsubstrate 9A and a gate insulating film 16 v provided on thesemiconductor substrate 9A. The gate insulating film 16 v is disposed onthe P-well region 10A. Although the details are described later, thegate insulating film 16 v is made of the same material as that of thegate insulating film 16 w provided in the writing element Mw1.

The gate insulating film 16 v in the driving element Mv1 is disposedbetween the floating gate FG1 in the portion where the driving elementMv1 is provided (i.e., specific region PA) and the semiconductorsubstrate 9A and has a film thickness larger than that of the tunnelinsulating film 15. The gate insulating film 16 v in the driving elementMv1 has an almost constant film thickness. No tunnel insulating film isprovided in the region where the gate insulating film 16 v is formed inthe driving element Mv1. Therefore, the surface where the gateinsulating film 16 v contacts the floating gate FG1 in the drivingelement Mv1 has a flat shape.

The tunnel insulating film 15 in this embodiment is formed in an openingportion in which an insulating film for forming the gate insulating film16 w is opened. Therefore, the gate insulating film 16 w in the writingelement Mw1 has a level difference due to an opening portion in theregion where the tunnel insulating film 15 is provided. Therefore, thecontact surface with the floating gate FG1 is flatter in the gateinsulating film 16 v in the driving element Mv1 than in the gateinsulating film 16 w in the writing element Mw1.

The driving element Mv1 is provided with the floating gate FG1 providedabove the semiconductor substrate 9A. The floating gate FG1 in theportion where the driving element Mv1 is provided (specific region PA)is continuously formed with the floating gate FG1 in the portion wherethe writing element Mw1 is provided. A part of the floating gate FG1 isdisposed on the gate insulating film 16 v. A region on the gateinsulating film 16 v is equivalent to the specific region PA of thefloating gate FG1.

The driving element Mv1 is provided with the control gate CG1 disposedabove the floating gate FG1 to be insulated from the floating gate FG1.The control gate CG1 provided in the driving element Mv1 is continuouslyformed with the control gate CG1 provided in the writing element Mw1.

The driving element Mv1 is provided with a drain region (an example ofthe second region) Dv1 provided in the semiconductor substrate 9A andformed to be electrically isolated from the first impurity diffusionregion IAa. Apart of the drain region Dv1 is disposed in a part belowthe floating gate FG1. The driving element Mv1 is provided with a sourceregion Sv1 provided in the semiconductor substrate 9A. The drain regionDv1 and the source region Sv1 are provided in the P-well region 10A. Thedrain region Dv1 and the source region Sv1 are defined by the currentflowing direction. Therefore, when a direction of passing a current isreversed to a direction of passing a current assumed in the nonvolatilestorage element M1 illustrated in FIGS. 1 and 2B, the drain region Dv1illustrated in FIGS. 1 and 2B serves as the source region Sv1 and thesource region Sv1 serves as the drain region Dv1.

As illustrated in FIG. 1, the source region Sv1 is formed in a part ofthe side (one of both sides) of the floating gate FG1 in the plan viewof the nonvolatile storage element M1. As illustrated in FIGS. 1 and 2B,the source region Sv1 has an LDD layer 12 vs and a source layer 13 vshaving an impurity concentration higher than that of the LDD layer 12vs. The source layer 13 vs is provided in the LDD layer 12 vs. Thesource layer 13 vs is provided in order to take an ohmic contact betweenthe source region Sv1 and a plug 51 vs (see FIG. 2B, details aredescribed later).

As illustrated in FIGS. 1 and 2B, the drain region Dv1 has a first drainlayer 11 v disposed in a part below the floating gate FG1, an N-type LDDlayer 12 vd disposed adjacent to the first drain layer 11 v, and asecond drain layer 13 vd having an impurity concentration higher thanthat of the LDD layer 12 vd. The second drain layer 13 vd is provided inthe LDD layer 12 vd. The second drain layer 13 vd is provided in orderto take an ohmic contact between the drain region Dv1 and a plug 51 vd(details are described later, see FIG. 2B).

As illustrated in FIG. 1, the drain region Dv is formed over a partbelow the floating gate FG1 and a part of the side (the other side ofboth sides) of the floating gate FG1 in the plan view of the nonvolatilestorage element M1. The first drain layer 11 v is provided in a partbelow the floating gate FG1. The LDD layer 12 vd and the second drainlayer 13 vd are provided in a part of the side of the floating gate FG1.The LDD layer 12 vd and the LDD layer 12 vs are provided with thefloating gate FG1 interposed therebetween in the plan view of thenonvolatile storage element M1. The first drain layer 11 v provided inthe driving element Mv1 has a width (length from one of both sides ofthe floating gate FG1 to the other side thereof) shorter than the widthof the diffusion layer 11 a provided in the writing element Mw1.

As illustrated in FIG. 2B, the dummy element Mm1 provided in thenonvolatile storage element M1 is provided with the semiconductorsubstrate 9A and a gate insulating film 16 m provided on thesemiconductor substrate 9A. The gate insulating film 16 m is disposed onthe P-well region 10A. Although the details are described later, thegate insulating film 16 m is made of the same material as that of thegate insulating film 16 w provided in the writing element Mw1 and thegate insulating film 16 v provided in the driving element Mv1.

The gate insulating film 16 m in the dummy element Mm1 is disposedbetween the floating gate FG1 in the portion where the dummy element Mm1is provided and the semiconductor substrate 9A and has a film thicknesslarger than that of the tunnel insulating film 15. The gate insulatingfilm 16 m in the dummy element Mm1 has an almost constant filmthickness. No tunnel insulating film is provided in the region where thegate insulating film 16 m is formed in the dummy element Mm1. Therefore,the surface where the gate insulating film 16 m contacts the floatinggate FG1 in the dummy element Mm1 has a flat shape. Since the gateinsulating film 16 m in the dummy element Mm1 does not have a leveldifference for forming a tunnel insulating film, the contact surfacewith the floating gate FG1 is flatter in the gate insulating film 16 mthan in the gate insulating film 16 w in the writing element Mw1.

The dummy element Mm1 is provided with the floating gate FG1 providedabove the semiconductor substrate 9A. The floating gate FG1 in theportion where the dummy element Mm1 is provided is continuously formedwith the floating gate FG1 in the portion where the writing element Mw1is provided and the floating gate FG1 in the portion (specific regionPA) where the driving element Mv1 is provided. A part of the floatinggate FG1 is disposed on the gate insulating film 16 m.

The dummy element Mm1 is provided with the control gate CG1 disposedabove the floating gate FG1 to be insulated from the floating gate FG1.The control gate CG1 provided in the dummy element Mm1 is continuouslyformed with the control gate CG1 provided in the writing element Mw1 andthe control gate CG1 provided in the driving element Mv1.

The dummy element Mm1 is provided with a drain region Dm1 provided inthe semiconductor substrate 9A and formed to be electrically isolatedfrom the first impurity diffusion region IAa. A part of the drain regionDm1 is disposed in a part below the floating gate FG1. The dummy elementMm1 is provided with a source region Sm1 provided in the semiconductorsubstrate 9A. The drain region Dm1 and the source region Sm1 areprovided in the P-well region 10A. The drain region Dm1 and the sourceregion Sm1 are defined by a current flowing direction. Therefore, when adirection of passing a current is reversed to a direction of passing acurrent assumed in the nonvolatile storage element M1 illustrated inFIGS. 1 and 2B, the drain region Dm1 illustrated in FIGS. 1 and 2Bserves as the source region Sm1 and the source region Sm1 serves as thedrain region Dm1.

As illustrated in FIG. 1, the source region Sm1 is provided in a part ofthe side (one of both sides) of the floating gate FG1 in the plan viewof the nonvolatile storage element M1. As illustrated in FIGS. 1 and 2B,the source region Sm1 has an LDD layer 12 ms and a source layer 13 mshaving an impurity concentration higher than that of the LDD layer 12ms. The source layer 13 ms is provided in the LDD layer 12 ms. Thesource layer 13 ms is provided in order to take an ohmic contact betweenthe source region Sm1 and a plug 51 ms (see FIG. 2B, details aredescribed later.).

As illustrated in FIGS. 1 and 2B, the drain region Dm1 has a first drainlayer 11 m disposed in a part below the floating gate FG1, an N-type LDDlayer 12 md disposed adjacent to the first drain layer 11 m, and asecond drain layer 13 md having an impurity concentration higher thanthat of the LDD layer 12 md. The second drain layer 13 md is provided inthe LDD layer 12 md. The second drain layer 13 md is provided in orderto take an ohmic contact between the drain region Dm1 and a plug 51 md(details are described later, see FIG. 2B).

As illustrated in FIG. 1, the drain region Dm1 is formed over a partbelow the floating gate FG1 and a part of the side (the other side ofboth sides) of the floating gate FG1 in the plan view of the nonvolatilestorage element M1. The first drain layer 11 m is provided in a partbelow the floating gate FG1. The LDD layer 12 md and the second drainlayer 13 md are provided in a part of the side of the floating gate FG1.The LDD layer 12 md and the LDD layer 12 ms are provided with thefloating gate FG1 interposed therebetween in the plan view of thenonvolatile storage element M1. The first drain layer 11 m provided inthe dummy element Mm1 has a width (length from one of both sides of thefloating gate FG1 to the other side thereof) shorter than the width ofthe diffusion layer 11 a provided in the writing element Mw1. The firstdrain layer 11 m provided in the dummy element Mm1 has the same width(length from one of both sides of the floating gate FG1 to the otherside thereof) as that of the first drain layer 11 v provided in thedriving element Mv1.

The floating gate FG1 in the portion where the writing element Mw1 isprovided, the floating gate FG1 in the portion (specific region PA)where the driving element Mv1 is provided, and the floating gate FG1 inthe portion where the dummy element Mm1 is provided are shared. Thefloating gate FG1 has an area of 30 μm² or more and 27000 μm² or less inthe plan view of the nonvolatile storage element M1. The lower limitvalue (30 μm² in this embodiment) of the area of the floating gate FG1is specified for differentiation from a case where a nonvolatile storageelement is used as a memory storing digital data. The area of thefloating gate FG1 in this embodiment is 1422 μm², for example, in theplan view of the nonvolatile storage element M1. The floating gate FG1in this embodiment has a rectangular shape in which the long sideextends in a direction where the writing element Mw1, the drivingelement Mv1, and the dummy element Mm1 are arranged in the plan view ofthe nonvolatile storage element M1. The floating gate FG1 may have theother shapes without being limited to the rectangular shape.

The control gate CG1 in the portion where the writing element Mw1 isprovided, the control gate CG1 in the portion where the driving elementMv1 is provided, and the control gate CG1 in the portion where the dummyelement Mm1 is provided are shared. The control gate CG1 has arectangular shape in which the long side extends in a direction wherethe writing element Mw1, the driving element Mv1, and the dummy elementMm1 are arranged in the plan view of the nonvolatile storage element M1.The control gate CG1 has a long side longer than that of the floatinggate FG1 and has a short side shorter than that of the floating gate FG1in the plan view of the nonvolatile storage element M1. Therefore, thecontrol gate CG1 has a region not overlapping with the floating gate FG1on the sides of both the short sides. The control gate CG1 may have theother shapes insofar as at least part thereof is disposed on thefloating gate FG1 without being limited to the rectangular shape.

As illustrated in FIGS. 2A to 2C, the nonvolatile storage element M1 isprovided with an insulating film 17 disposed on the floating gate FG1and a sidewall 18 (see FIGS. 2A and 2B) formed around the insulatingfilm 17. The control gate CG1 is formed on the insulating film 17. Thefloating gate FG1 and the control gate CG1 are insulated by theinsulating film 17. The insulating film 17 is configured combining asilicon oxide film and a silicon nitriding film and has anoxide/nitride/oxide (ONO) structure. The insulating film 17 is providedcovering the upper surface and the side surface of the floating gate FG1and the side surfaces of the gate insulating films 16 w, 16 v, and 16 m.The insulating film 17 is disposed covering the floating gate FG1 overthe writing element Mw1, the driving element Mv1, and the dummy elementMm1. The sidewall 18 is disposed surrounding the insulating film 17 in alevel difference portion of the lateral wall of the insulating film 17over the writing element Mw1, the driving element Mv1, and the dummyelement Mm1. Therefore, the writing element Mw1, the driving elementMv1, and the dummy element Mm1 each have the insulating film 17 and thesidewall 18.

The nonvolatile storage element M1 has halogen (for example, fluorine)distributing in at least part of the tunnel insulating film 15, the gateinsulating films 16 w, 16 v, and 16 m, and the insulating film 17. Inthis embodiment, halogen is contained in all of the tunnel insulatingfilm 15, the gate insulating films 16 w, 16 v, and 16 m, and theinsulating film 17. Due to the fact that the tunnel insulating film 15contains halogen (for example, fluorine), the defect density of thetunnel insulating film 15 decreases.

As illustrated in FIGS. 2A and 2B, the nonvolatile storage element M1 isprovided with a sidewall 19 formed around the control gate CG1. Thesidewall 19 is disposed surrounding the lateral wall of the control gateCG1 over the writing element Mw1, the driving element Mv1, and the dummyelement Mm1. Therefore, the writing element Mw1, the driving elementMv1, and the dummy element Mm1 each have the sidewall 19.

The nonvolatile storage element M1 is provided with the control gate CG1and an interlayer insulating film 61 formed on the element formationsurface of the semiconductor substrate 9A. The interlayer insulatingfilm 61 is formed at least in regions where the insulating film 17, thesidewalls 18 and 19, the first impurity diffusion region IAa, the secondimpurity diffusion region IAb, the drain region Dv1 and Dm1, the sourceregion Sv1 and Sm1, and the element isolation region 41 are provided.The interlayer insulating film 61 exhibits a function as a protectivefilm protecting the control gate CG1, the first impurity diffusionregion IAa, the second impurity diffusion region IAb, the drain regionsDv1 and Dm1, the source regions Sv1 and Sm1, and the like.

As illustrated in FIGS. 1 and 2C, the nonvolatile storage element M1 hasa plug 51 g embedded in an opening portion exposing a part of thecontrol gate CG1 to the bottom surface and formed in the interlayerinsulating film 61 and a metal wiring line 52 g (not illustrated inFIG. 1) electrically connected to the plug 51 g and formed on theinterlayer insulating film 61. The plug 51 g is provided in a regionwhere the control gate CG1 does not overlap with the floating gate FG1.The metal wiring line 52 g and the control gate CG1 are electricallyconnected through the plug 51 g. This makes it possible to apply avoltage of a predetermined level to the control gate CG1 from the metalwiring line 52 g through the plug 51 g.

As illustrated in FIG. 2B, the driving element Mv1 is provided with theplug 51 vd embedded in an opening portion exposing a part of the seconddrain layer 13 vd to the bottom surface and formed in the interlayerinsulating film 61 and a metal wiring line 52 vd electrically connectedto the plug 51 vd and formed on the interlayer insulating film 61. Themetal wiring line 52 vd and the drain region Dv1 are electricallyconnected through the plug 51 vd. This makes it possible to apply avoltage of a predetermined level to the drain region Dv1 from the metalwiring line 52 nd through the plug 51 vd.

The driving element Mv1 is provided with the plug 51 vs embedded in anopening portion exposing a part of the source layer 13 vs to the bottomsurface and formed in the interlayer insulating film 61 and a metalwiring line 52 vs electrically connected to the plug 51 vs and formed onthe interlayer insulating film 61. The metal wiring line 52 vs and thesource region Sv1 are electrically connected through the plug 51 vs.This makes it possible to apply a voltage of a predetermined level tothe source region Sv1 from the metal wiring line 52 vs through the plug51 vs.

As illustrated in FIG. 2B, the dummy element Mm1 is provided with a plug51 md embedded in an opening portion exposing a part of the second drainlayer 13 md to the bottom surface and formed in the interlayerinsulating film 61 and a metal wiring line 52 md electrically connectedto the plug 51 md and formed on the interlayer insulating film 61. Themetal wiring line 52 md and the drain region Dm1 are electricallyconnected through the plug 51 md. This makes it possible to apply avoltage of a predetermined level to the drain region Dm1 from the metalwiring line 52 md through the plug 51 md.

The dummy element Mm1 is provided with a plug 51 ms embedded in anopening portion exposing a part of the source layer 13 ms to the bottomsurface and formed in the interlayer insulating film 61 and a metalwiring line 52 ms electrically connected to the plug 51 ms and formed onthe interlayer insulating film 61. The metal wiring line 52 ms and thesource region Sm1 are electrically connected through the plug 51 ms.This makes it possible to apply a voltage of a predetermined level tothe source region Sm1 from the metal wiring line 52 ms through the plug51 ms.

As illustrated in FIG. 2A, the writing element Mw1 is provided with aplug 51 a embedded in an opening portion exposing a part of the contactlayer 13 a to the bottom surface and formed in the interlayer insulatingfilm 61 and a metal wiring line 52 a electrically connected to the plug51 a and formed on the interlayer insulating film 61. The metal wiringline 52 a and the first impurity diffusion region IAa are electricallyconnected through the plug 51 a. This makes it possible to apply avoltage of a predetermined level to the first impurity diffusion regionIAa from the metal wiring line 52 a through the plug 51 a.

The writing element Mw1 is provided with a plug 51 b embedded in anopening portion exposing a part of the contact layer 13 b to the bottomsurface and formed in the interlayer insulating film 61 and a metalwiring line 52 b electrically connected to the plug 51 b and formed onthe interlayer insulating film 61. The metal wiring line 52 b and thesecond impurity diffusion region IAb are electrically connected throughthe plug 51 b. This makes it possible to apply a voltage of apredetermined level to the second impurity diffusion region IAb from themetal wiring line 52 b through the plug 51 b.

As illustrated in FIG. 2B, the driving element Mv1 configures a MOSFET.The nonvolatile storage element M1 is configured to operate with theother circuits by causing the driving element Mv1 to function as aMOSFET. More specifically, when the nonvolatile storage element M1operates with the other circuits, a current path is formed in the drainregion Dv1 and the source region Sv1 of the driving element Mv1.

On the other hand, as illustrated in FIG. 2A, the writing element Mw1has the plug 51 a and the metal wiring line 52 a electrically connectedto the first impurity diffusion region IAa and has the plug 51 b and themetal wiring line 52 b electrically connected to the second impuritydiffusion region IAb. While a predetermined voltage is applied to themetal wiring line 52 a, the metal wiring line 52 b is brought into anopen state. Therefore, the second impurity diffusion region IAb is inthe floating state and the writing element Mw1 does not configure aMOSFET. The writing element Mw1 functions as a voltage applicationelement in the writing of injecting a charge into the floating gate FG2or emitting a charge from the floating gate FG2 using the first impuritydiffusion region IAa. More specifically, the first impurity diffusionregion IAa functions as a writing voltage application region and thedrain region Dv1 functions as a drain region of the driving MOSFET.

As illustrated in FIG. 2B, the dummy element Mm1 configures a MOSFET.The dummy element Mm1 may function as a MOSFET and may be used as anelement operating with the other circuits together with the drivingelement Mv1. The dummy element Mm1 may be used as an alternative elementfor a damaged driving element Mv1. More specifically, a current path isformed in the drain region Dm1 and the source region Sm1 of the dummyelement Mm1 as necessary when the nonvolatile storage element M1operates with the other circuits. Therefore, the drain region Dm1functions as a drain region of the driving MOSFET in some cases.

Next, a method for adjusting the threshold voltage Vth of thenonvolatile storage element M1 is described.

For example, when 19 V is applied to the control gate CG1 and 0 V isapplied to the first impurity diffusion region IAa, an electron isinjected into the floating gate FG1 through the tunnel insulating film15, and then the floating gate FG1 is brought into a negatively chargedstate. In this state, the floating gate FG1 acts in a direction ofsuppressing an electric field applied to the gate insulating films 16 vand 16 m when a positive bias is applied to the control gate CG1.Therefore, the threshold voltage Vth increases in the driving elementMv1 and the dummy element Mm1 of the nonvolatile storage element M1 andthe driving element Mv1 and the dummy element Mm1 function asenhancement type MOSFETs.

On the other hand, when 0 V is applied to the control gate CG1 and 19 Vis applied to the drain region D1, for example, an electron is extractedfrom the floating gate FG1 through the tunnel insulating film 15, andthen the floating gate FG1 is brought into a positively charged state.In this state, the floating gate FG1 acts in a direction of intensifyingan electric field applied to the gate insulating films 16 v and 16 mwhen a positive bias is applied to the control gate CG1. Therefore, thethreshold voltage Vth decreases in the driving element Mv1 and the dummyelement Mm1 of the nonvolatile storage element M1 and the drivingelement Mv1 and the dummy element Mm1 function as depression typeMOSFETs. Thus, the threshold voltage Vth of the nonvolatile storageelement M1 can be adjusted to a desired value by controlling theinjection of a charge into the floating gate FG1 or the extraction of acharge from the floating gate FG1.

Next, a threshold voltage Vth fluctuation (retention degradation) due tocharge leakage from a floating gate is described. Hereinafter, theretention degradation is described mainly taking a phenomenon that anelectron inside the floating gate leaks to the outside of the floatinggate as an example. The retention degradation similarly occurs also inthe case of a phenomenon that an electron is injected into the inside ofthe floating gate from the outside of the floating gate (substantially,a phenomenon that a hole inside the floating gate leaks to the outsideof the floating gate).

The retention degradation includes two modes of first mode retentiondegradation and second mode retention degradation. The first moderetention degradation is a threshold voltage Vth fluctuation caused bythe leakage of a charge from the floating gate through a defectgenerated in a tunnel insulating film. The defect in the tunnelinsulating film is generated due to the fact that the tunnel insulatingfilm is damaged by a charge passing in injecting a charge into thefloating gate (in writing). The second retention degradation is athreshold voltage Vth fluctuation occurring caused by the fact that anelectron in the floating gate excited by thermal energy jumps over theenergy barrier of the tunnel insulating film and leaks.

First, the first mode retention degradation is described. The first moderetention degradation is a phenomenon that a charge leakages from thefloating gate through a defect in the tunnel insulating film. Therefore,the degree of the first mode retention degradation is dependent on thedefect density in the tunnel insulating film. The defect in the tunnelinsulating film is generated in the charge injection into the floatinggate (in writing). Furthermore, the first mode retention degradation hasa feature that the temperature dependency is low. According to themechanism described above, the amount of charges passing through thetunnel insulating film in the writing may be reduced in order tosuppress the first mode retention degradation. When the thresholdvoltage Vth of the nonvolatile storage element is adjusted to a certainspecific value, the total amount of charges injected into the floatinggate depends on the area of the floating gate and becomes larger whenthe area is larger. On the other hand, a charge moves through a regionwhere the tunnel insulating film is formed. Therefore, the amount ofcharges passing through the tunnel insulating film per unit area thereofbecomes smaller when the area of the tunnel insulating film is larger.Therefore, the generation of the defect in the tunnel insulating film isfurther suppressed when the ratio of the area of the tunnel insulatingfilm to the area of the floating gate is larger.

FIGS. 3A and 3B are graphs illustrating the experiment results of thearea ratio of the tunnel insulating film to the floating gate and thefluctuation life time of the threshold voltage Vth due to the first moderetention degradation at room temperature. This experiment is anaccelerated test of adjusting the threshold voltage Vth of nonvolatilestorage elements different in the area ratio of the tunnel insulatingfilm to the floating gate to a predetermined threshold voltage Vth, andthen measuring the fluctuation life time of the threshold voltage Vthafter allowed to stand for predetermined time. For this experiment,measurement samples of nonvolatile storage elements having the samestructure as that of the nonvolatile storage element M1 illustrated inFIGS. 1 and 2A to 2C were used. As the measurement samples, three kindsof nonvolatile storage elements of a nonvolatile storage element Ahaving an area ratio of a tunnel insulating film to a floating gate of0.000176, a nonvolatile storage element B having the area ratio of0.001582, and a nonvolatile storage element C having the area ratio of0.017721 were used. 4000 nonvolatile storage elements A were preparedand allowed to stand under a 27° C. atmosphere. When 168 hours, 500hours, and 1000 hours passed after allowed to stand, the thresholdvoltage Vth of each of the 4000 nonvolatile storage elements A wasmeasured, and then the fluctuation amounts of the threshold voltages Vthat each of the standing time were calculated. The nonvolatile storageelements B and C were similarly measured for the threshold voltage Vthat each of the three standing time above using 4000 measurement samplesfor each of the nonvolatile storage elements B and C, and then thefluctuation amounts of the threshold voltages Vth before and after thestanding were calculated.

“Tunnel area/Floating gate area” of the horizontal axis of each of thegraphs illustrated in FIGS. 3A and 3B represents the area ratio of thetunnel insulating film to the floating gate. In this experiment, thearea ratio of the tunnel insulating film to the floating gate isadjusted by fixing the area of the floating gate and changing the areaof the tunnel insulating film. “Operating time [year]” of the verticalaxis of each of the graphs illustrated in FIGS. 3A and 3B represents aconverted value of the operating time of each nonvolatile storageelement based on the time dependency (dependency on each standing time(168 hours, 500 hours, and 1000 hours)) of the threshold voltage Vth ineach nonvolatile storage element. The ⋄ marks in the graph illustratedin FIG. 3A indicate the operating time in which the ratio of themeasurement samples having a threshold voltage Vth fluctuation of lessthan 100 mV is 99.87% (equivalent to 3 σ on one side) of all themeasurement samples used for the experiment for each of the nonvolatilestorage elements A, B, and C. The left ⋄ mark indicates the timedependency of the threshold voltage Vth of the nonvolatile storageelement A, the center ⋄ mark indicates the time dependency of thethreshold voltage Vth of the nonvolatile storage element B, and theright ⋄ mark indicates the time dependency of the threshold voltage Vthof the nonvolatile storage element C. The straight line connecting the ⋄marks in the graph illustrated in FIG. 3A is an approximate straightline based on the operating time. The ⋄ marks in the graph illustratedin FIG. 3B indicate the operating time in which the ratio of themeasurement samples having a threshold voltage Vth fluctuation of lessthan 100 mV is 99.997% (equivalent to 4 σ on one side) of all themeasurement samples used for the experiment for each of the nonvolatilestorage elements A, B, and C. The left ⋄ mark indicates the timedependency of the threshold voltage Vth of the nonvolatile storageelement A, the center ⋄ mark indicates the time dependency of thethreshold voltage Vth of the nonvolatile storage element B, and theright ⋄ mark indicates the time dependency of the threshold voltage Vthof the nonvolatile storage element C. The straight line connecting the ⋄marks in the graph illustrated in FIG. 3B is an approximate straightline based on the operating time.

Herein, the operating time in which the threshold voltage Vth of thenonvolatile storage element fluctuates by 100 mV is defined as the lifetime. As indicated by the dashed straight line in FIG. 3A, it is foundthat the area ratio of the tunnel insulating film to the floating gateneeds to be 0.002 or more in order for 99.87% of all the measurementsamples (equivalent to 3 σ on one side) to secure the life time of tenyears or more. As indicated by the dashed straight line in FIG. 3B, itis found that the area ratio of the tunnel insulating film to thefloating gate needs to be 0.011 or more in order for 99.997% of all themeasurement samples (equivalent to 4 σ on one side) to secure the lifetime of ten years or more. Thus, the nonvolatile storage element mayhave a floating gate and a tunnel insulating film in which the arearatio of the tunnel insulating film to the floating gate is 0.002 ormore. When the area ratio of the tunnel insulating film to the floatinggate is 0.011 or more and 1 or less, the first mode retentiondegradation (low temperature retention) is further improved. Therefore,when an analog circuit in which the nonvolatile storage element is usedrequires a highly accurate voltage, the nonvolatile storage element mayhave a floating gate and a tunnel insulating film in which the arearatio of the tunnel insulating film to the floating gate is 0.011 ormore.

Next, the second mode retention degradation is described. The secondmode retention degradation is caused by the fact that a charge in thefloating gate excited by thermal energy jumps over the energy barrier ofthe tunnel insulating film and leaks (hereinafter sometimes referred toas “charge leakage”). The charge leakage may occur anywhere in thetunnel insulating film region having the same energy barrier. Morespecifically, the occurrence probability of the charge leakage dependson the area of the tunnel insulating film and can be reduced by reducingthe area. Moreover, the phenomenon of the charge leakage is relevant tothe thermal excitation of an electron, and therefore is furtheraccelerated when the temperature is higher.

FIGS. 4A and 4B are graphs illustrating the experiment results of thearea of the tunnel insulating film and the fluctuation life time of thethreshold voltage Vth of the nonvolatile storage element due to thesecond mode retention degradation at 70° C. This experiment is anaccelerated test of adjusting a threshold voltage to a predeterminedthreshold voltage Vth, and then measuring the threshold voltage Vthafter standing of the nonvolatile storage element allowed to stand undercertain conditions. For this experiment, measurement samples ofnonvolatile storage elements having the same structure as that of thenonvolatile storage element M1 illustrated in FIG. 1 were used. In thisexperiment, 4000 nonvolatile storage elements adjusted to thepredetermined threshold voltage Vth were allowed to stand under each ofthe three conditions of 24 hours under a 200° C. atmosphere, ten hoursunder a 250° C. atmosphere, and 24 hours under a 250° C. atmosphere. Thethreshold voltages Vth of the nonvolatile storage elements afterstanding under each of the conditions were measured, and then thefluctuation amounts of the threshold voltages Vth before and after thestanding were calculated.

“Tunnel area [μm²]” of the horizontal axis of each of the graphsillustrated in FIGS. 4A and 4B represents the area (area in a plan viewof the nonvolatile storage element) of the tunnel insulating filmprovided in the nonvolatile storage element. “Operating time [year]” ofthe vertical axis of each of the graphs illustrated in FIGS. 4A and 4Brepresents the converted value of the operating time of each nonvolatilestorage element based on the time dependency and the temperaturedependency (Arrhenius equation) of the threshold voltage Vth in eachnonvolatile element. The ⋄ mark in the graph illustrated in FIG. 4Aindicates the operating time in which the ratio of the measurementsamples having a threshold voltage Vth fluctuation of less than 100 mVis 99.87% (equivalent to 3 σ on the one side) of all the measurementsamples used for the experiment. The straight line connecting the ⋄marks in the graph illustrated in FIG. 4A is an approximate straightline based on the operating time. The ⋄ marks in the graph illustratedin FIG. 4B indicate the operating time in which the ratio of themeasurement samples having a threshold voltage Vth fluctuation of lessthan 100 mV is 99.997% (equivalent to 4 σ on one side) of all themeasurement samples used for the experiment. The straight lineconnecting the ⋄ marks in the graph illustrated in FIG. 4B is anapproximate straight line based on the operating time.

Herein, the operating time in which the threshold voltage Vth of thenonvolatile storage element fluctuates by 100 mV is defined as the lifetime. As indicated by the dashed straight line in FIG. 4A, it is foundthat the area of the tunnel insulating film (tunnel area) needs to be 54μm² or less in order for 99.87% (equivalent to 3 σ on one side) of allthe measurement samples to secure the life time of ten years or more. Asindicated by the dashed straight line in FIG. 4B, it is found that thearea of the tunnel insulating film (tunnel area) needs to be 40 μm² orless in order for 99.997% (equivalent to 4 σ on one side) of all themeasurement samples to secure the life time of ten years or more. Thus,the nonvolatile storage element may have a tunnel insulating film havingan area of 54 μm² or less. When the area of the tunnel insulating filmis 40 μm² or less, the second mode retention degradation (normalretention) is further improved. Therefore, when an analog circuit inwhich the nonvolatile storage element is used requires a highly accuratevoltage, the nonvolatile storage element may have a tunnel insulatingfilm having an area of 40 μm² or less.

FIGS. 5A and 5B are graphs illustrating the adaptive region of the areaconfiguration of the floating gate and the tunnel insulating filmprovided in the nonvolatile storage element according to thisembodiment. FIG. 5A is the graph created based on the numerical valuesobtained from the graphs illustrated in FIGS. 3A and 4A. Morespecifically, FIG. 5A illustrates the adaptive region of the areaconfiguration in which it is expected that the nonvolatile storageelement can secure the life time of ten years or more with theprobability of 99.87%. FIG. 5B is the graph created based on thenumerical values obtained from the graphs illustrated in FIGS. 3B and4B. More specifically, FIG. 5B illustrates the adaptive region of thearea configuration in which it is expected that the nonvolatile storageelement can secure the life time of ten years or more with theprobability of 99.997%. Hereinafter, the adaptive region of the areaconfiguration of the floating gate and the tunnel insulating film inwhich it is expected that 99.87% (3 σ on one side) of nonvolatilestorage elements distributed in the market can secure the life time often years or more is referred to as “standard adaptive region”. Theadaptive region of the area configuration of the floating gate and thetunnel insulating film in which it is expected that 99.997% (4 σ on oneside) of nonvolatile storage elements distributed in the market cansecure the life time of ten years or more is referred to as “highlyaccurate adaptive region”.

“Floating gate area [μm²]” of the horizontal axis of each of the graphsillustrated in FIGS. 5A and 5B represents the area of the floating gateprovided in the nonvolatile storage element (area in a plan view of thenonvolatile storage element). “Tunnel area [m²]” of the vertical axis ofeach of the graphs illustrated in FIGS. 5A and 5B represents the area ofthe tunnel insulating film provided in the nonvolatile storage element(area in the plan view of the nonvolatile storage element). A dashedstraight line F1 in the graph illustrated in each of FIGS. 5A and 5Bindicates the lower limit value of the floating gate area. A dashedstraight line T1 in the graph illustrated in FIG. 5A indicates the upperlimit value of the tunnel area in the standard adaptive region. A dashedstraight line TF1 in the graph illustrated in FIG. 5A indicates acharacteristic when the area ratio of the tunnel insulating film to thefloating gate is 0.002. A dashed straight line TF2 in the graphillustrated in each of FIGS. 5A and 5B indicates a characteristic whenthe area ratio of the tunnel insulating film to the floating gate is 1.A dashed straight line T2 in the graph illustrated in FIG. 5B indicatesthe upper limit value of the tunnel area in the highly accurate adaptiveregion. A dashed straight line TF3 in the graph illustrated in FIG. 5Bindicates a characteristic when the area ratio of the tunnel insulatingfilm to the floating gate is 0.011. The ◯ marks in the graphsillustrated in FIGS. 5A and 5B indicate the floating gate area and thetunnel area of the nonvolatile storage element M1 according to thisembodiment and the Δ marks indicate an example of the floating gate areaand the tunnel area of a memory cell storing digital data (0 or 1).

The straight lines TF1, TF2, and TF3 are straight lines determined basedon the area ratio of the tunnel insulating film to the floating gate inwhich the first mode retention degradation described with reference toFIGS. 3A and 3B is suppressed. The straight lines T1 and T2 are straightlines determined based on the area of the tunnel insulating film inwhich the second mode retention degradation described with reference toFIGS. 4A and 4B is suppressed. The straight line F1 is a straight linedetermined based on the lower limit value of the area of the floatinggate for differentiation from a case where a nonvolatile storage elementof the same structure as that of the nonvolatile storage element Maccording to this embodiment is used as a memory storing digital data.

Therefore, as illustrated in FIG. 5A, a region surrounded by thestraight line T1, the straight line F1, the straight line TF1, and thestraight line TF2 is the standard adaptive region of the floating gateand the tunnel insulating film. The regions on the straight line T1, thestraight line F1, the straight line TF1, and the straight line TF2 areincluded in the standard adaptive region. The nonvolatile storageelement having the floating gate and the tunnel insulating film havingan area included in the standard adaptive region becomes an element inwhich the probability that the first mode retention degradation and thesecond mode retention degradation do not occur is expected to be 99.87%even when the operating time has reached ten years in total.

As illustrated in FIG. 5B, a region surrounded by the straight line T2,the straight line F1, the straight line TF3, and the straight line TF2is the highly accurate adaptive region of the floating gate and thetunnel insulating film. The regions on the straight line T2, thestraight line F1, the straight line TF2, and the straight line TF3 areincluded in the highly accurate adaptive region. The nonvolatile storageelement having the floating gate and the tunnel insulating film havingan area included in the highly accurate adaptive region becomes anelement in which the probability that the first mode retentiondegradation and the second mode retention degradation do not occur isexpected to be 99.997% even when the operating time has reached tenyears in total.

The area of the floating gate FG1 of the nonvolatile storage element M1according to this embodiment is 1422 μm² and the area of the tunnelinsulating film 15 thereof is 25.2 μm². On the other hand, the area ofthe floating gate of the memory cell for digital data is 6.24 μm² andthe area of the tunnel insulating film thereof is 0.25 μm². Therefore,as illustrated in FIGS. 5A and 5B, the nonvolatile storage element M1 isincluded in both the standard adaptive region and the highly accurateadaptive region. The memory cell for digital data is not included in thestandard adaptive region and the highly accurate adaptive region.

From the description above, by setting the area of the tunnel insulatingfilm to 54 μm² or less when the FLOTOX nonvolatile storage element isused as the MOSFET having a floating gate area of 30 μm² or more in ananalog circuit, the probability that a charge in the floating gateexcited by thermal energy jumps over the energy barrier of the tunnelinsulating film and leaks is suppressed and the second mode retentiondegradation can be suppressed. Moreover, by setting the area ratio ofthe tunnel insulating film to the floating gate to 0.002 or more whenthe nonvolatile storage element is used as the MOSFET having a floatinggate area of 30 μm² or more, the amount of charges passing through thetunnel insulating film per unit area thereof decreases and the firstmode retention degradation can also be suppressed. This makes itpossible for the nonvolatile storage element to minimize the influenceon analog circuit characteristics caused by the first mode retentiondegradation and the second mode retention degradation.

Therefore, the adaptive region of the area configuration of the floatinggate and the tunnel insulating film is a region demarcated by the twostraight lines based on the lower limit value and the upper limit valueof the area ratio of the tunnel insulating film to the floating gaterequired in order to suppress the first mode retention degradation, thestraight line based on the upper limit value of the tunnel area requiredin order to suppress the second mode retention degradation, and thestraight line based on the lower limit value of the floating gate area.The peaks of the adaptive region of the area configuration of thefloating gate and the tunnel insulating film are the intersectionbetween the two straight lines based on the lower limit value and theupper limit value of the area ratio and the straight line based on theupper limit value of the tunnel area and the intersection between thetwo straight lines and the straight line based on the lower limit valueof the floating gate area.

The upper limit value of the area of the tunnel insulating film is avalue fluctuating depending on to what extent the life time of thenonvolatile storage element is set. The lower limit value of the area ofthe floating gate is a value fluctuating depending on the use of thenonvolatile storage element. Therefore, the lower limit value of thearea of the floating gate may be smaller than the lower limit valueillustrated in FIG. 5 depending on the driving capability required forthe analog circuit provided with the nonvolatile storage element.Accordingly, the upper limit value of the tunnel area and the lowerlimit value of the floating area demarcating the adaptive region of thearea configuration of the floating gate and the tunnel insulating filmillustrated in FIGS. 5A and 5B may be an example and the other valuesmay be acceptable.

The nonvolatile storage element according to this embodiment produced tobe included in the adaptive region of the area configuration of thefloating gate and the tunnel insulating film described above canminimize the influence on analog circuit characteristics caused by thefirst mode retention degradation and the second mode retentiondegradation.

Herein, the specific region PA which is the region of the floating gateFG1 in the portion where the driving element Mv1 is provided isdescribed using FIGS. 6 to 8 referring to FIGS. 1 and 2A to 2C. Thehorizontal axis of the graph illustrated in FIG. 6 represents agate-source voltage Vgs [V] between a control gate and a source regionprovided in a nonvolatile storage element having the same structure asthat the driving element Mv1. The vertical axis of the graph illustratedin FIG. 6 represents a drain current Ids [A] of the nonvolatile storageelement. On the left side in FIG. 6, the characteristic when a value ofthe threshold voltage Vth of the nonvolatile storage element is adjustedto 0 V is illustrated. On the right side in FIG. 6, the characteristicwhen the value of the threshold voltage Vth of the nonvolatile storageelement is adjusted to 3.5 V is illustrated. “T: −40” illustrated inFIG. 6 illustrates the characteristic of the drain current Ids to thegate-source voltage Vgs of the nonvolatile storage element when theambient temperature is −40° C. “T: 30” illustrated in FIG. 6 illustratesthe characteristic of the drain current Ids to the gate-source voltageVgs of the nonvolatile storage element when the ambient temperature is30° C. “T: 90” illustrated in FIG. 6 illustrates the characteristic ofthe drain current Ids to the gate-source voltage Vgs of the nonvolatilestorage element when the ambient temperature is 90° C.

As illustrated in FIG. 6, the nonvolatile storage element having thesame structure as the driving element Mv1 has a characteristic that thecurrent value of the drain current Ids to the ambient temperature isreversed with a predetermined value of the gate-source voltage Vgs asthe boundary. More specifically, the current value of the drain currentIds of the nonvolatile storage element is larger at a high ambienttemperature than at a low ambient temperature in a range where thegate-source voltage Vgs is lower than the predetermined value, thecurrent value is identical irrespective of the ambient temperature atthe predetermined value, and the current value is smaller at a highambient temperature than at a low ambient temperature in a range wherethe gate-source voltage Vgs is higher than the predetermined value.Hereinafter, drain currents at which the threshold voltages are adjustedto the same value and current values of which are identical to eachother even when the ambient temperature is different in a plurality ofnonvolatile storage elements are referred to as “temperature independentcurrent”.

In the actual operation of the nonvolatile storage element M1, thedriving element Mv1 mainly operates. Therefore, due to the fact that thedriving element Mv1 is configured to operate by a temperatureindependent current Itid, an improvement of temperature characteristicsof the nonvolatile storage element M1 can be achieved.

Furthermore, the nonvolatile storage element M1 is a technology for lowpower consumption. Therefore, when a temperature independent currentItid of the nonvolatile storage element M1 (i.e., temperatureindependent current Itid of the driving element Mv) is in a low currentconsumption region (for example, several nA or less) as illustrated inFIG. 6, the nonvolatile storage element M1 having low power consumptionand excellent also in temperature characteristics can be achieved.

Between the temperature independent current Itid of the driving elementMv1 and the channel width and the channel length of the driving elementMv1, i.e., the gate width W and the gate length L in the specific regionPA of the floating gate FG1, the relationship illustrated in thefollowing expression (1) is established.

$\begin{matrix}{\left\lbrack {{Expression}\mspace{14mu} 1} \right\rbrack \mspace{585mu}} & \; \\{{Itid} = {A \times \frac{W^{\alpha}}{L^{\beta}}}} & (1)\end{matrix}$

In Expression (1), “A” indicates the constant. Next, the constant A, anindex α of the gate width W, and an index β of the gate length L inExpression (1) are described. The constant A, the index α, and the indexβ are determined by producing a plurality of NMOS samples which have thesame structure as that of the driving element Mv1 and in which eitherthe gate width W or the gate length L is varied and using a measurementvalue of the temperature independent current of each sample.

Table 1 illustrates the measurement results of the temperatureindependent current to the gate width of the NMOS having the samestructure as that of the driving element Mv1. “W [μm]” illustrated inthe upper row in Table 1 indicates the gate width of the NMOS, “Itid[A]” illustrated in the upper row indicates the temperature independentcurrent, and “A” illustrated in the upper row indicates the constant Ain Expression (1). A method for calculating the constant A is describedlater. The gate length L of each sample is 10 μm. The temperatureindependent current was measured with a state that a voltage of 0.1 Vwas applied between the source and the drain of the NMOS.

TABLE 1 W [μm] Itid [A] A 0.24 3.7 × 10⁻⁹ 1.1 × 10⁻⁵ 0.28 5.3 × 10⁻⁹ 1.2× 10⁻⁵ 0.32 6.8 × 10⁻⁹ 1.1 × 10⁻⁵ 0.36 8.7 × 10⁻⁹ 1.1 × 10⁻⁵ 1.00 7.6 ×10⁻⁸ 1.3 × 10⁻⁵ 10.0 7.4 × 10⁻⁶ 1.1 × 10⁻⁵ (L = 10 μm)

As illustrated in Table 1, the temperature independent current wasmeasured for six kinds of the samples when the gate width W of the NMOSis in the range of 0.24 μm to 10.0 μm. FIG. 7 illustrates therelationship between the gate width W and the temperature independentcurrent Itid created using the measurement results of the temperatureindependent current illustrated in Table 1. The horizontal axis of thegraph illustrated in FIG. 7 represents the gate width W [μm] (i.e., W[μm] illustrated in Table 1) of the NMOS used as the measurement sample.The vertical axis of the graph illustrated in FIG. 7 represents thetemperature independent current Itid [A] of the NMOS (i.e., Itid [A]illustrated in Table 1). The graph illustrated in FIG. 7 is a log-loggraph. The dotted line illustrated in FIG. 7 is a power approximationcurve connecting the measurement points. An expression illustrated inFIG. 7 is an expression indicating the power approximation curve. “x” ofthe expression is the gate width W and “y” of the expression is thetemperature independent current Itid.

As illustrated in FIG. 7, the temperature independent current Itid ofthe NMOS varies depending on the gate width W of the NMOS when the gatelength of the NMOS is fixed. The temperature independent current Itid ofthe NMOS has a characteristic of increasing with an increase in the gatewidth W of the NMOS and being given by “7×10⁻⁸ W^(2.036)”. Thecoefficient (index) in which the temperature independent current Itid ofthe NMOS depends on the gate width W of the NMOS is the index α inExpression (1). Therefore, the α value is 2.036.

Table 2 illustrates the measurement results of the temperatureindependent current to the gate length of the NMOS having the samestructure as that the driving element Mv1. “1/L [/μm]” illustrated inthe top row in Table 2 indicates the reciprocal of the gate length ofthe NMOS, “Itid [A]” illustrated in the top row indicates a temperatureindependent current, and “A” illustrated in the top row indicates theconstant A in Expression (1). “Ave.” illustrated in the bottom row inTable 2 indicates an average value of the constants A. Methods forcalculating the constant A and the average value of the constants A aredescribed later. The gate width W of each sample is 10 μm. Thetemperature independent current was measured with a state that a voltageof 0.1 V was applied between the source and the drain of the NMOS.

TABLE 2 1/L [μm] Itid [A] A 1.67 3.5 × 10⁻³ 1.0 × 10⁻⁵ 1.47 2.6 × 10⁻³1.0 × 10⁻⁵ 1.39 2.4 × 10⁻³ 1.1 × 10⁻⁵ 1.32 2.2 × 10⁻³ 1.1 × 10⁻⁵ 1.251.9 × 10⁻³ 1.0 × 10⁻⁵ 1.14 1.5 × 10⁻³ 1.1 × 10⁻⁵ 1.00 1.1 × 10⁻³ 1.0 ×10⁻⁵ 0.50 2.2 × 10⁻⁴ 9.3 × 10⁻⁶ 0.20 3.0 × 10⁻⁵ 9.8 × 10⁻⁶ 0.10 7.4 ×10⁻⁶ 1.1 × 10⁻⁵ Ave. 1.1 × 10⁻⁵ (W = 10 μm)

As illustrated in Table 2, the temperature independent current wasmeasured for ten kinds of samples when the reciprocal of the gate lengthL of the NMOS is in the range of 1.67 μm to 0.10 μm. FIG. 8 illustratesthe relationship between the reciprocal of the gate length L and thetemperature independent current Itid created using the measurementresults of the temperature independent current illustrated in Table 2.The horizontal axis of the graph illustrated in FIG. 8 represents thereciprocal 1/L [/μm] (i.e., 1/L [/μm] illustrated in Table 2) of thegate length L of the NMOS used as the measurement sample. The verticalaxis of the graph illustrated in FIG. 8 represents the temperatureindependent current Itid [A] (i.e., Itid [A] illustrated in Table 2) ofthe NMOS. The graph illustrated in FIG. 8 is a log-log graph. The dottedline illustrated in FIG. 8 is a power approximation curve connecting themeasurement points. An expression illustrated in FIG. 8 is an expressionindicating the power approximation curve. “x” of the expression is thereciprocal 1/L of the gate length L and “y” of the expression is thetemperature independent current Itid.

As illustrated in FIG. 8, the temperature independent current Itid ofthe NMOS varies depending on the gate length L of the NMOS when the gatewidth of the NMOS is fixed. The temperature independent current Itid ofthe NMOS has a characteristic of increasing with an increase in thereciprocal 1/L of the gate length L (i.e., with a reduction in the gatelength L of the NMOS) and being given by “1.1×10⁻⁸ (1/L)^(2.215)”. Thecoefficient (index) in which the temperature independent current Itid ofthe NMOS depends on the reciprocal 1/L of the gate length L of the NMOSis the index β in Expression (1). Therefore, the β value is 2.215.

When the values of the index α and the index β obtained by theabove-described measurement are assigned to Expression (1), thefollowing expression (2) is obtained.

$\begin{matrix}{\left\lbrack {{Expression}\mspace{14mu} 2} \right\rbrack \mspace{585mu}} & \; \\{{Itid} = {A \times \frac{W^{2.036}}{L^{2.215}}}} & (2)\end{matrix}$

When Expression (2) is modified, the following expression (3) isobtained.

$\begin{matrix}{\left\lbrack {{Expression}\mspace{14mu} 3} \right\rbrack \mspace{585mu}} & \; \\{\frac{Itid}{A} = \frac{W^{2.036}}{L^{2.215}}} & (3)\end{matrix}$

The value of the constant A illustrated in Table 1 is calculated byassigning the gate width W, the gate length L, and the temperatureindependent current Itid illustrated in Table 1 to Expression (2). Forexample, A=1.1×10⁻⁵ illustrated in the second row of Table 1 iscalculated by assigning W=0.24 μm, Itid=3.7×10⁹ A, and L=10 μmillustrated in the second row of Table 1 to Expression (2). Similarly,the value of the constant A illustrated in Table 2 is calculated byassigning the reciprocal 1/L of the gate length L, the gate width W, andthe temperature independent current Itid illustrated in Table 2 toExpression (2). For example, A=1.0×10⁻⁵ illustrated in the second row ofTable 2 is calculated by assigning 1/L=1.67 (/μm), Itid=3.5×10⁻³ A, andW=10 μm illustrated in the second row of Table 2 to Expression (2). Theaverage value (numerical value indicated on the right side of “Ave.”) ofthe constants A illustrated in Table 2 is the average value of sixconstant A values illustrated in Table 1 and ten constant A valuesillustrated in Table 2. In this embodiment, the average value is definedas the constant A value.

In this embodiment, an operating current of the driving element Mv1 isassumed to be 1 nA or less. Therefore, with respect to the conditionthat the temperature independent current Itid is equal to or less thanthe operating current, the following expression (4) is obtained byassigning 1 nA which is the assumed maximum operating current and theaverage value “1.1×10⁻⁵” of the constants A illustrated in Table 2 toItid of Expression (3).

$\begin{matrix}{{{Expression}\mspace{14mu} (4)}\mspace{585mu}} & \; \\{{9.28 \times 10^{- 5}} \geq \frac{W^{2.036}}{L^{2.215}}} & (4)\end{matrix}$

Therefore, when the gate length of the specific region PA of thefloating gate FG1 is defined as L (see FIG. 1), the gate width W and thegate length L of the specific region PA of the floating gate FG1 maysatisfy the relationship of Expression (4) described above. Due to thefact that the gate width W and the gate length L of the specific regionPA of the floating gate FG1 of the driving element Mv1 satisfy therelationship of Expression (4) described above, the drain current Ids ofthe driving element Mv1 is hard to depend on the ambient temperature andthe value is 1 nA or less, and therefore the nonvolatile storage elementM1 can achieve an improvement of temperature stability and a reductionin power consumption.

When Expression (2) is solved for the gate length L, the followingexpression (5) is obtained.

$\begin{matrix}{{{Expression}\mspace{14mu} (5)}\mspace{585mu}} & \; \\{L = \left( \frac{Itid}{A \times W^{2.036}} \right)^{\frac{1}{- 2.215}}} & (5)\end{matrix}$

Herein, an area S of the specific region PA of the floating gate FG1 isgiven by the product (W×L) of the gate width W and the gate length L.The condition of the area S of the specific region PA in which the gatewidth W is 0.5 μm of the minimum value and the temperature independentcurrent Itid is equal to or less than the operating current (1 nA) is17.5 μm² or more, when S=W×L and Expression (5) are used. Morespecifically, the region of the floating gate FG1 in the driving elementMv1, i.e., a specific region PA, may have an area of 17.5 μm² or moreand may satisfy the relationship of Expression (4). Thus, the draincurrent Ids of the driving element Mv1 is hard to depend on the ambienttemperature and the value is 1 nA or less at the minimum value (0.5 μm)of a 0.5 μm generation manufacturing process which is a next generationmanufacturing process, and therefore the nonvolatile storage element M1can achieve an improvement of temperature stability and a reduction inpower consumption.

The temperature independent current Itid of Expression (2) can beexpressed by the following expression (6) when the area S of thespecific region PA is used.

$\begin{matrix}{{{Expression}\mspace{14mu} (6)}\mspace{585mu}} & \; \\{{Itid} = {A \times \frac{W^{4.251}}{S^{2.215}}}} & (6)\end{matrix}$

It is supposed that the entire floating gate FG1 has an area larger than30 μm² when the area of the floating gate FG1 specified fordifferentiation from a case where a nonvolatile storage element is usedas a memory storing digital data is 30 μm² or more and 27000 μm² orless. In this case, when it is supposed that the area of the specificregion PA of the floating gate FG1 is 30 μm² or more and the gate widthW is 0.5 μm of the minimum value, the temperature independent currentItid is 3.0×10⁻¹⁰ A or less, which is smaller than the minimum valueassumed in this embodiment. Thus, when the entire floating gate FG1 hasan area larger 30 μm², the area of the specific region PA of thefloating gate FG1 may be 30 μm² or more. Thus, the nonvolatile storageelement M1 can achieve a further reduction in power consumption.

(Method for Manufacturing Nonvolatile Storage Element)

Next, a method for manufacturing the nonvolatile storage element M1according to this embodiment is described with reference to FIG. 1 andFIGS. 2A to 2C and FIGS. 9A to 9F to 18A to 18C. FIGS. 9A to 9F to 18Ato 18C illustrate manufacturing processes of one nonvolatile storageelement of a plurality of nonvolatile storage elements simultaneouslyformed on one semiconductor substrate. FIGS. 9A and 9D, 10A and 10D, 11Aand 11D, 12A, 13A and 13D, 14A and 14D, 15A and 15D, 16A and 16D, 17Aand 17D, and 18A illustrate cross sections of manufacturing processes(i.e., cross sections of manufacturing process of the writing elementMw1) of the nonvolatile storage element M1 cut along the A-A line inFIG. 1. FIGS. 9B and 9E, 10B and 10E, 11B and 11E, 12B, 13B and 13E, 14Band 14E, 15B and 15E, 16B and 16E, 17B and 17E, and 18B illustrate crosssections of manufacturing processes (i.e., cross sections ofmanufacturing process of the driving element Mv1 (and the dummy elementMm1)) of the nonvolatile storage element M1 cut along the B1-B1 line(and B2-B2 line) in FIG. 1. FIGS. 9C and 9F, 10C and 10F, 11C and 11F,12C, 13C and 13F, 14C and 14F, 15C and 15F, 16C and 16F, 17C and 17F,and 18C illustrate cross sections of manufacturing processes (i.e.,cross sections of manufacturing process of a portion where the plug 51 gis provided) of the nonvolatile storage element M1 cut along the C-Cline in FIG. 1. In FIGS. 9A, 9B, and 9C, 9D, 9E, and 9F, 10A, 10B, and10C, 10D, 10E, and 10F, 11A, 11B, and 11C, 11D, 11E, and 11F, 12A, 12Band 12C, 13A, 13B, and 13C, 13D, 13E, and 13F, 14A, 14B, and 14C, 14D,14E, and 14F, 15A, 15B, and 15C, 15D, 15E, and 15F, 16A, 16B, and 16C,16D, 16E, and 16F, 17A, 17B, and 17C, 17D, 17E, and 17F, and 18A, 18B,and 18C the manufacturing processes of the nonvolatile storage element Mare illustrated in this order in a time series.

First, the P-type semiconductor substrate 9A is thermally oxidized toform an oxide film 10 z of silicon dioxide having a film thickness of300 Å on the surface of the semiconductor substrate 9A as illustrated inFIGS. 9A, 9B, and 9C. Next, boron is injected into an upper portion ofthe semiconductor substrate 9A to form an impurity layer. Next, theimpurity layer is thermally diffused by 1200° C. furnace annealing toform the P-well region 10A in the upper portion of the semiconductorsubstrate 9A as illustrated in FIGS. 9A, 9B, and 9C.

Next, the oxide film 10 z is removed, a pad oxide film is formed on thesemiconductor substrate 9A, and then silicon nitride is deposited on thepad oxide film to form a nitride film. Next, photoresist is applied ontothe nitride film, the photoresist is exposed and developed, and then aresist mask covering a region where a nonvolatile storage element isfinally formed is formed.

Next, dry etching of the nitride film is performed with the resist maskas a mask to remove the nitride film in a region other than a regionbelow the resist mask. Subsequently, the resist mask is removed by dryashing. Next, thermally oxidization is performed until the filmthickness of the pad oxide film of a region not covered with the nitridefilm reaches 7000 Å by the LOCOS method.

Next, wet etching of the nitride film is performed with hot phosphoricacid. Next, the pad oxide film is removed with fluoric acid until theP-well region 10A in the region where the nitride film is formed isexposed. Thus, as illustrated in FIGS. 9D, 9E, and 9F, the elementisolation region 41 is formed in the predetermined region on thesemiconductor substrate 9A.

Next, the semiconductor substrate 9A is thermally oxidized, silicondioxide is deposited in the region where the P-well region 10A isexposed with a thickness of 480 Å, and an oxide film 16 z partiallyserving as the gate insulating films 16 w, 16 v, and 16 m is formed onthe entire surface of the semiconductor substrate 9A as illustrated inFIGS. 10A and 10B. As illustrated in FIGS. 10A, 10B, and 10C, the oxidefilm 16 z is formed in the region where the P-well region 10A is exposedand is hardly formed on the oxide film configuring the element isolationregion 41. Next, photoresist is applied to the entire surface of thesemiconductor substrate 9A including the oxide film 16 z, and then thephotoresist is exposed and developed. Thus, as illustrated in FIGS. 10A,10B, and 10C, a resist mask RM11 is formed in which the oxide film 16 zin a region where the diffusion layer 11 a, the first drain layer 11 v,and the first drain layer 11 m (see FIGS. 1 and 2A to 2C) are formed inthe future is at least exposed. The resist mask RM11 has an openingregion continuously formed over the region where the diffusion layer 11a, the first drain layer 11 v, and the first drain layer 11 m are formedin the future. In a part of the opening region, the oxide film 16 z isexposed. In the remaining portion of the opening region, the elementisolation region 41 is exposed.

Next, arsenic ions are injected with the resist mask RM11 as a mask. Thearsenic ion is injected with such energy that the arsenic ion can passthrough the oxide film 16 z to reach the P-well region 10A but cannotreach the P-well region 10A passing through the element isolation region41. Thus, The diffusion layer 11 a is formed in the P-well region 10Abelow the oxide film 16 z opened by the resist mask RM11 as illustratedin FIG. 10D. As illustrated in FIG. 10E, The first drain layer 11 v isformed in the P-well region 10A below the oxide film 16 z opened by theresist mask RM11. Furthermore, as illustrated in FIG. 10F, The firstdrain layer 11 m is formed in the P-well region 10A below the oxide film16 z opened by the resist mask RM11. The diffusion layer 11 a, the firstdrain layer 11 v, and the first drain layer 11 m are simultaneouslyformed in a state of being isolated from each other. Thereafter, theresist mask RM11 is removed by dry etching.

Next, photoresist is applied to the entire surface of the semiconductorsubstrate 9A, and then the photoresist is exposed and developed. Thus,as illustrated in FIGS. 11A, 11B, and 11C, a resist mask RM15 exposingthe oxide film 16 z in a region where the tunnel insulating film 15 (seeFIG. 2) is formed in the future is formed.

Next, wet etching of the oxide film 16 z is performed with the resistmask RM15 as a mask. Thus, as illustrated in FIGS. 11D, 11E, and 11F, anopening portion 15 z is formed in which the oxide film 16 z in a regionwhere the tunnel insulating film 15 is formed in the future is removed.Then, the resist mask RM15 is removed by dry etching.

Next, the semiconductor substrate 9A is thermally oxidized, silicondioxide is formed until the film thickness reaches 98 Å in the openingportion 15 z in which the P-well region 10A is exposed, and then, asillustrated in FIG. 12A, the tunnel insulating film 15 is formed inapart on the P-well region 10A in a region where the writing element Mw1(see FIG. 2) is formed in the future. On the other hand, as illustratedin FIG. 12B, no tunnel insulating film is formed on the P-well region10A in a region where the driving element Mv1 and the dummy element Mm1(see FIGS. 2A to 2C) are formed in the future and the oxide film 16 zhaving an almost constant film thickness remains. As illustrated in FIG.12C, the oxide film 16 z is not present in a region where the plug 51 gis formed in the future, and therefore the element isolation region 41is exposed.

Next, polysilicon is deposited on the semiconductor substrate 9Aincluding the top of the tunnel insulating film 15 with a thickness of2000 Å, and then a polysilicon film FGz partially serving as thefloating gate FG1 (see FIGS. 1 and 2A to 2C) in the future is formed asillustrated in FIGS. 13A, 13B, and 13C. Next, photoresist is applied tothe entire surface of the semiconductor substrate 9A, and then thephotoresist is exposed and developed. Thus, as illustrated in FIGS. 13A,13B, and 13C, a resist mask RMf exposing the polysilicon film FGz in aregion where the floating gate FG1 is formed in the future is formed.

Next, as illustrated in FIGS. 13D, 13E, and 13F, fluorine ions areinjected into the polysilicon film FGz with the resist mask RMf as amask. Thus, a fluorine existing region FA in which a relatively largeamount of fluorine is present is formed in the region of the polysiliconfilm FGz not covered with the resist mask RMf. Thereafter, the resistmask RMf is removed by dry ashing.

Next, photoresist is applied to the entire surface of the semiconductorsubstrate 9A, and then the photoresist is exposed and developed. Thus,as illustrated in FIGS. 14A, 14B, and 14C, a resist mask RMfg coveringthe polysilicon film FGz in a region where the floating gate FG1 and thegate insulating films 16 w, 16 v, and 16 m are formed in the future isformed.

Next, as illustrated in FIGS. 14D, 14E, and 14F, the polysilicon filmFGz and the oxide film 16 z in a portion other than a portion below theresist mask RMfg are successively removed by dry etching with the resistmask RMfg as a mask. Thus, the floating gate FG1 and the gate insulatingfilms 16 w, 16 v, and 16 m are formed. By the formation of the floatinggate FG1, the charge inlet 14 is formed at a position corresponding tothe tunnel insulating film 15. Thereafter, the resist mask RMfg isremoved by dry ashing.

Next, as illustrated in FIGS. 15A, 15B, and 15C, an oxide/nitride/oxide(ONO) film 17 z covering the floating gate FG1 and the gate insulatingfilms 16 w, 16 v, and 16 m and partially serving as the insulating film17 (see FIG. 2) in the future is formed. The ONO film 17 z is formed bysuccessively performing thermal oxidation of the semiconductor substrate9A and deposition and thermal oxidation of the nitride film. By the heatin the formation of the ONO film 17 z, the fluorine in the floating gateFG1 can be rapidly taken into the ONO film 17 z, the gate insulatingfilms 16 w, 16 v, and 16 m, and the tunnel insulating film 15 to besegregated. More specifically, as indicated by the curved arrow towardthe outside from the fluorine existing region FA in FIGS. 15A and 15B,the fluorine can be distributed with a high concentration in all thedirections surrounding the floating gate FG1 from the fluorine existingregion FA by the heat in the formation of the ONO film 17 z.

As illustrated in FIGS. 15D, 15E, and 15F, polysilicon is formed on theentire surface of the ONO film 17 z after the formation of the ONO film17 z to form a polysilicon film CGz partially serving as the controlgate CG1 (see FIGS. 1 and 2) in the future.

Next, as illustrated in FIGS. 16A, 16B, and 16C, silicon dioxide isdeposited on the entire surface of the polysilicon film CGz to form anoxide film CGy. Next, photoresist is applied to the entire surface ofthe oxide film CGy, and then the photoresist is exposed and developed.Thus, as illustrated in FIGS. 16A, 16B, and 16C, a resist mask RMccovering the oxide film CGy in a region where the control gate CG1 isformed in the future is formed.

Next, as illustrated in FIGS. 16D, 16E, and 16F, the oxide film CGy in aportion other than a portion below the resist mask RMc is removed by dryetching with the resist mask RMc as a mask. Thus, a mask for forming thecontrol gate CG1 is formed by the oxide film CGy. Thereafter, the resistmask RMc is removed by dry etching.

Next, as illustrated in FIGS. 17A, 17B, and 17C, the polysilicon filmCGz in a portion other than a portion below the oxide film CGy isremoved by dry etching with the oxide film CGy as a mask. Thus, thecontrol gate CG1 is formed.

Next, arsenic ions are injected into the P-well region 10A with thefloating gate FG1 as a mask. Thus, as illustrated in FIG. 17D, the LDDlayer 12 b is formed in a part of the P-well region 10A on one of bothsides of the floating gate FG1 in a region where the writing element Mw1is formed in the future and the LDD layer 12 a is formed in a part ofthe P-well region 10A on the other side of both sides of the floatinggate FG1 in the region. As illustrated in FIG. 17E, simultaneously withthe formation of the LDD layers 12 a and 12 b, the LDD layer 12 vs isformed in a part of the P-well region 10A on one of both sides of thefloating gate FG1 in a region where the driving element Mv1 is formed inthe future and the LDD layer 12 vd is formed in a part of the P-wellregion 10A on the other side of both sides of the floating gate FG1 inthe region. As illustrated in FIG. 17E, simultaneously with theformation of the LDD layers 12 a and 12 b, the LDD layer 12 ms is formedin a part of the P-well region 10A on one of both sides of the floatinggate FG1 in a region where the dummy element Mm1 is formed in the futureand the LDD layer 12 md is formed in a part of the P-well region 10A onthe other side of both sides of the floating gate FG1 in the region. Onthe other hand, a region where the plug 51 g is finally formed iscovered with the control gate CG1, and therefore no LDD layer is formedin the P-well region 10A in the region as illustrated in FIG. 17F.Thereafter, the oxide film CGy is removed by dry ashing.

Next, an oxide film of silicon dioxide is formed on the entire surfaceon the semiconductor substrate 9A including the control gate CG1 and theONO film 17 z. Next, the oxide film and the ONO film 17 z are partiallydry etched while leaving the periphery of each of the control gate CG1and the ONO film 17 z. Thus, as illustrated in FIGS. 18A and 18C, theinsulating film 17 covering the floating gate FG1 is formed, thesidewall 18 is formed in the periphery of the insulating film 17, andthe sidewall 19 is formed in the periphery of the control gate CG1. Asillustrated in FIG. 18C, the insulating film 17 and continuously formedwith the insulating film 17 covering the floating gate FG1 is formed ina region where the plug 51 g is formed in the future.

Next, arsenic ions are injected into the LDD layers 12 a, 12 b, 12 vs,12 vd, 12 ms, and 12 md with the control gate CG1, the insulating film17, and the sidewalls 18 and 19 as a mask. Thus, as illustrated in FIG.2A, the contact layer 13 b is formed in a partial region of the LDDlayer 12 b and the second impurity diffusion region IAb is formed in theP-well region 10A on one of both sides of the floating gate FG1 in aregion where the writing element Mw1 is formed in the future. Thecontact layer 13 a is formed in a partial region of the LDD layer 12 aand the first impurity diffusion region IAa is formed in a part of theP-well region 10A below and on the other side of both sides of thefloating gate FG1 in a region where the writing element Mw1 is formed inthe future.

As illustrated in FIG. 2B, the source layer 13 v is formed in a partialregion of the LDD layer 12 vs and the source region Sv1 is formed in theP-well region 10A on one of both sides of the floating gate FG1 in aregion where the driving element Mv1 is formed in the future. The seconddrain layer 13 vd is formed in a partial region of the LDD layer 12 vdand the drain region Dv1 is formed in a part of the P-well region 10Abelow and on the other side of both sides of the floating gate FG1 in aregion where the driving element Mv1 is formed in the future.

As illustrated in FIG. 2B, the source layer 13 ms is formed in a partialregion of the LDD layer 12 ms and the source region Sm1 is formed in theP-well region 10A on one of both sides of the floating gate FG1 in aregion where the dummy element Mm1 is formed in the future. The seconddrain layer 13 md is formed in a partial region of the LDD layer 12 mdand the drain region Dm1 is formed in a part of the P-well region 10Abelow and on the other side of both sides of the floating gate FG1 in aregion where the dummy element Mm1 is formed in the future.

Next, as illustrated in FIGS. 2A to 2C, an insulating interlayerinsulating film 61 is formed on the entire surface of the semiconductorsubstrate 9A including the control gate CG1, the floating gate FG1, thefirst impurity diffusion region IAa, the second impurity diffusionregion IAb, the source regions Sv1 and Sm1, the drain regions Dv1 andDm1, and the like.

Next, as illustrated in FIG. 2A, opening portions opening a part of thecontact layers 13 a and 13 b to the bottom surface are formed in theinterlayer insulating film 61. Simultaneously with the formation of theopening portions, opening portions opening a part of the source layers13 vs and 13 ms to the bottom surface and opening portions opening apart of the second drain layers 13 vd and 13 md to the bottom surfaceare formed in the interlayer insulating film 61 as illustrated in FIG.2B. Simultaneously with the formation of these opening portions, anopening portion opening a part of the control gate CG1 in a region notoverlapping with the floating gate FG1 to the bottom surface is formedin the interlayer insulating film 61 as illustrated in FIG. 2C.

Next, as illustrated in FIG. 2A, the plugs 51 a and 51 b made of metalmaterials are embedded in the opening portions on the contact layers 13a and 13 b. As illustrated in FIG. 2B, simultaneously with the embeddingof the plugs 51 a and 51 b, the plugs 51 vd and 51 md made of metalmaterials are embedded in the opening portions on the second drainlayers 13 vd and 13 md, respectively and the plugs 51 vs and 51 ms madeof metal materials are embedded in the opening portions formed on thesource layers 13 vs and 13 ms, respectively. As illustrated in FIG. 2C,the plug 51 g made of a metal material is embedded in the openingportion on the control gate CG1 simultaneously with the formation of theplugs 51 a and 51 b.

Next, as illustrated in FIG. 2A, the metal wiring line 52 a is formed onthe plug 51 a exposed to the interlayer insulating film 61 and the metalwiring line 52 b is formed on the plug 51 b exposed to the interlayerinsulating film 61. Thus, the writing element Mw1 is completed.Simultaneously with the formation of the metal wiring lines 52 a and 52b, the metal wiring line 52 vs is formed on the plug 51 vs exposed tothe interlayer insulating film 61 and the metal wiring line 52 nd isformed on the plug 51 vd exposed to the interlayer insulating film 61 asillustrated in FIG. 2B. Thus, the driving element Mv1 is completed.Simultaneously with the formation of the metal wiring lines 52 a and 52b, the metal wiring line 52 ms is formed on the plug 51 ms exposed tothe interlayer insulating film 61 and the metal wiring line 52 md isformed on the plug 51 md exposed to the interlayer insulating film 61 asillustrated in FIG. 2B. Thus, the dummy element Mm1 is completed.Simultaneously with the formation of the metal wiring line 52 a and 52b, the metal wiring line 52 g is formed on the plug 51 g exposed to theinterlayer insulating film 61 as illustrated in FIG. 2C. Thus, thenonvolatile storage element M1 provided with the writing element Mw1,the driving element Mv1, and the dummy element Mm1 is completed.

(Reference Voltage Generation Circuit Provided with Nonvolatile StorageElement)

Next, a reference voltage generation circuit is described with referenceto FIGS. 19 to 22 as an example of the analog circuit provided with thenonvolatile storage element M1 according to this embodiment. The analogcircuit to which the nonvolatile storage element M1 is applied is notlimited to the reference voltage generation circuit insofar as thecircuit is a circuit using the nonvolatile storage element M1 in ananalog manner. For example, the nonvolatile storage element M1 iseffective also in analog circuits requiring accuracy in the thresholdvoltage of the MOSFET, such as an operational amplifier circuit and acomparator circuit.

Next, the circuit configuration of a reference voltage generationcircuit RC3 is described with reference to FIG. 19.

As illustrated in FIG. 19, the reference voltage generation circuit RC3in this embodiment is provided with a nonvolatile storage element M31and a nonvolatile storage element M33 connected in series. Thenonvolatile storage element M31 and the nonvolatile storage element M33each have the same configuration as that of the nonvolatile storageelement M1 according to this embodiment illustrated in FIGS. 1 and 2A to2C. The nonvolatile storage element M31 is provided with a writingelement Mw31, a driving element Mv31, and a dummy element Mm31. Thenonvolatile storage element M33 is provided with a writing element Mw33,a driving element Mv33, and a dummy element Mm33. The writing elementMw31 and the writing element Mw33 have the same configuration as that ofthe writing element Mw1 illustrated in FIGS. 1 and 2A. The drivingelement Mv31 and the driving element Mv33 have the same configuration asthat of the driving element Mv1 illustrated in FIGS. 1 and 2B. The dummyelement Mm31 and the dummy element Mm33 have the same configuration asthat of the dummy element Mm1 illustrated in FIGS. 1 and 2C.

The control gate CG1 of the driving element Mv31, the control gate CG1of the dummy element Mm31, and the control gate CG1 of the writingelement Mw31 are continuously formed and shared. The floating gate FG1of the driving element Mv31, the floating gate FG1 of the dummy elementMm31, and the floating gate FG1 of the writing element Mw31 arecontinuously formed and shared. The charge inlet 14 provided in thewriting element Mw31 is formed in a region not in contact with a currentpath formed in the driving element Mv31. The charge inlet 14 provided inthe writing element Mw31 is formed in a region not in contact with acurrent path formed in the dummy element Mm31. The charge inlet 14provided in the writing element Mw31 is formed in a region not incontact with a current path including the drain region Dv1 and thesource region Sv1 of the driving element Mv31. The charge inlet 14provided in the writing element Mw31 is formed in a region not incontact with a current path including the drain region Dm1 and thesource region Sm1 of the dummy element Mm31.

The control gate CG1 of the driving element Mv33, the control gate CG1of the dummy element Mm33, and the control gate CG1 of the writingelement Mw33 are continuously formed and shared. The floating gate FG1of the driving element Mv33, the floating gate FG1 of the dummy elementMm33, and the floating gate FG1 of the writing element Mw33 arecontinuously formed and shared. The charge inlet 14 provided in thewriting element Mw33 is formed in a region not in contact with a currentpath formed in the driving element Mv33. The charge inlet 14 provided inthe writing element Mw33 is formed in a region not in contact with acurrent path formed in the dummy element Mm33. The charge inlet 14provided in the writing element Mw33 is formed in a region not incontact with a current path including the drain region Dv1 and thesource region Sv1 of the driving element Mv33. The charge inlet 14provided in the writing element Mw33 is formed in a region not incontact with a current path including the drain region Dm1 and thesource region Sm1 of the dummy element Mm33.

When the reference voltage generation circuit RC3 operates with theother circuits, the driving element Mv31 and the driving element Mv33are connected in series between a driving power supply terminal Vdd1 anda low voltage supply terminal Vss. More specifically, the drain regionDv1 of the driving element Mv31 is connected to the driving power supplyterminal Vdd1. The source region Sv1 of the driving element Mv33 isconnected to the low voltage supply terminal Vss. The source region Sv1of the driving element Mv31 and the drain region Dv1 of the drivingelement Mv33 are connected.

In the reference voltage generation circuit RC3, the dummy element Mm31is not used and is in the floating state. Therefore, when the referencevoltage generation circuit RC3 operates with the other circuits, boththe source region Sm1 and the drain region Dm1 of the dummy element Mm31are not connected to the driving power supply terminal Vdd1 and the lowvoltage supply terminal Vss.

In the reference voltage generation circuit RC3, the dummy element Mm33is not used and is in the floating state. Therefore, when the referencevoltage generation circuit RC3 operates with the other circuits, boththe source region Sm1 and the drain region Dm1 of the dummy element Mm33are not connected to the driving power supply terminal Vdd1 and the lowvoltage supply terminal Vss.

The writing element Mw31 is provided with the first impurity diffusionregion IAa partially disposed below the floating gate FG1. The referencevoltage generation circuit RC3 is provided with a switch SW31 having oneterminal connected to the first impurity diffusion region IAa of thewriting element Mw31. One of the other terminals of the switch SW31 isconnected to a low voltage supply terminal Vss and the other one of theother terminals of the switch SW31 is connected to an applicationterminal of a pulse voltage Vpp. The reference voltage generationcircuit RC3 is configured to be able to apply either one of the lowvoltage Vss and the pulse voltage Vpp to the first impurity diffusionregion IAa of the writing element Mw31 by switching the switch SW31 asappropriate. To the second impurity diffusion region IAb of the writingelement Mw31, a predetermined switch is not connected and the secondimpurity diffusion region IAb is in the floating state.

The writing element Mw33 is provided with the first impurity diffusionregion IAa partially disposed below the floating gate FG1. The referencevoltage generation circuit RC3 is provided with a switch SW32 having oneterminal connected to the first impurity diffusion region IAa of thewriting element Mw33. One of the other terminals of the switch SW32 isconnected to a low voltage supply terminal Vss and the other one of theother terminals of the switch SW32 is connected to an applicationterminal of a pulse voltage Vpp. The reference voltage generationcircuit RC3 is configured to be able to apply either one of the lowvoltage Vss and the pulse voltage Vpp to the first impurity diffusionregion IAa of the writing element Mw33 by switching the switch SW32 asappropriate. To the second impurity diffusion region IAb of the writingelement Mw33, a predetermined switch is not connected and the secondimpurity diffusion region IAb is in the floating state.

The reference voltage generation circuit RC3 is provided with a switchSW35 and a switch SW37 connected in series between the control gate CG1of the writing element Mw31 and the control gate CG1 of the writingelement Mw33. The other terminals of the switch SW35 and the switch SW37are connected to each other. The other terminals of the switch SW35 andthe switch SW37 are connected to a connection portion where the sourceregion Sv1 of the driving element Mv31 and the drain region Dv1 of thedriving element Mv33 are connected to each other. The reference voltagegeneration circuit RC3 is provided with a voltage output terminal OUTconnected to the connection portion and outputting a reference voltageVREF.

The reference voltage generation circuit RC3 is provided with a switchSW33 having one terminal connected to the control gate CG1 of thewriting element Mw31 and a switch SW39 having one terminal connected tothe other terminal of the switch SW33. One of the other terminals of theswitch SW39 is connected to an application terminal of a pulse voltageVpp and the other one of the other terminals of the switch SW39 isconnected to a low voltage supply terminal Vss. The reference voltagegeneration circuit RC3 is configured to be able to apply either one ofthe pulse voltage Vpp and the low voltage Vss to the control gate CG1 ofthe writing element Mw31 by switching the switch SW39 as appropriatewhen the switch SW33 is in a connection state (short-circuit state).

The reference voltage generation circuit RC3 is provided with a switchSW34 having one terminal connected to the control gate CG1 of thewriting element Mw33 and a switch SW30 having one terminal connected tothe other terminal of the switch SW34. One of the other terminals of theswitch SW30 is connected to an application terminal of a pulse voltageVpp and the other one of the other terminals of the switch SW30 isconnected to a low voltage supply terminal Vss. The reference voltagegeneration circuit RC3 is configured to be able to apply either one ofthe pulse voltage Vpp and the low voltage Vss to the control gate CG1 ofthe writing element Mw33 by switching the switch SW30 as appropriatewhen the switch SW34 is in a connection state (short-circuit state).

The writing element Mw31 is a region present for injecting a charge intothe floating gates FG1 of the driving element Mv31 and the dummy elementMm31 and does not pass a current as a transistor. Similarly, the writingelement Mw33 is a region present for injecting a charge into thefloating gates FG2 of the driving element Mv33 and the dummy elementMm33 and does not pass a current as a transistor. Therefore, the writingelement Mw31 and the writing element Mw33 need not to have a sourceregion or a drain region and the form is not limited insofar as astructure of having a charge inlet is provided.

Next, a method for adjusting the threshold voltage of the referencevoltage generation circuit RC3 is described using FIGS. 20 and 21referring to FIG. 19.

As illustrated in FIGS. 20 and 21, the reference voltage generationcircuit RC3 is connected to a high voltage supply terminal Vdd in placeof the driving power supply terminal Vdd1 when injecting a charge intothe floating gate FG1 or emitting a charge from the floating gate FG1.In the reference voltage generation circuit RC3, a charge is injectedinto the floating gate FG1 through the writing elements Mw31 and Mw33 inthe charge injection. As illustrated in FIG. 19, when operating thereference voltage generation circuit RC3, a current flows through thedriving elements Mv31 and Mv33. In the reference voltage generationcircuit RC3, the nonvolatile storage element M31 side (i.e., writingelement Mw31, driving element Mv31, and dummy element Mm31) is in adepression state and the nonvolatile storage element M33 side (i.e.,writing element Mw33, driving element Mv33, and dummy element Mm33) isin an enhancement state.

As illustrated in FIG. 19, the reference voltage generation circuit RC3switches the switches SW30 to SW35, SW37, and SW39 to the followingstates when generating the reference voltage VREF.

Switch SW30: Arbitrary (low voltage supply terminal Vss side in FIG. 19)

Switch SW31: Low voltage supply terminal Vss side

Switch SW32: Low voltage supply terminal Vss side

Switch SW33: Connection state (short-circuit state)

Switches SW34 and SW35: Open state (open-circuit state)

Switch SW37: Connection state (short-circuit state)

Switch SW39: Low voltage supply terminal Vss side

As illustrated in FIG. 20, the reference voltage generation circuit RC3switches the switches SW30 to SW35, SW37, and SW39 to the followingstates in rewriting for bringing the nonvolatile storage element M31side (i.e., writing element Mw31, driving element Mv31, and dummyelement Mm31) into a depression state. Herein, a case where thethreshold voltage before the adjustment on the nonvolatile storageelement M31 side is higher than the threshold voltage after theadjustment is taken as an example.

Switch SW30: Arbitrary (low voltage supply terminal Vss side in FIG. 20)

Switch SW31: Pulse voltage Vpp side

Switch SW32: Low voltage supply terminal Vss side

Switch SW33: Connection state (short-circuit state)

Switch SW34: Open stat (open-circuit state)

Switches SW35 and SW37: Open stat (open-circuit state)

Switch SW39: Low voltage supply terminal Vss side

Therefore, the pulse voltage Vpp is applied to the first impuritydiffusion region IAa of the writing element Mw31 and the low voltage Vssis applied to the control gate CG1, and therefore an electron is emittedto the first impurity diffusion region IAa from the floating gate FG1through the charge inlet 14 configured in the region where the tunnelinsulating film is formed. Thus, the threshold voltage of the writingelement Mw31 becomes low. On the contrary, when the low voltage Vss isapplied to the first impurity diffusion region IAa of the writingelement Mw31 and the pulse voltage Vpp is applied to the control gateCG1, an electron is injected into the floating gate FG1 from the firstimpurity diffusion region IAa through the charge inlet 14. Thus, thethreshold voltage of the writing element Mw31 becomes high. The controlgate CG1 and the floating gate FG1 are shared by the writing elementMw31, the driving element Mv31, and the dummy element Mm31. Therefore,the driving element Mv31 and the dummy element Mm31 each have the samethreshold voltage as that of the writing element Mw31.

As illustrated in FIG. 21, the reference voltage generation circuit RC3switches the switches SW30 to SW35, SW37, and SW39 to the followingstates in rewriting for bringing the nonvolatile storage element M33side (i.e., writing element Mw33, driving element Mv33, and dummyelement Mm33) into an enhancement state. Herein, a case where thethreshold voltage before the adjustment on the nonvolatile storageelement M33 side is lower than the threshold voltage after theadjustment is taken as an example.

Switch SW30: Pulse voltage Vpp side

Switch SW31: Low voltage supply terminal Vss side

Switch SW32: Low voltage supply terminal Vss sde

Switch SW33: Open state (open-circuit state)

Switch SW34: Connection state (short-circuit state)

Switches SW35 and SW37: Open state (open-circuit state)

Switch SW39: Arbitrary (low voltage supply terminal Vss side in FIG. 21)

Therefore, the low voltage Vss is applied to the first impuritydiffusion region IAa of the writing element Mw33 and the pulse voltageVpp is applied to the control gate CG1, and therefore an electron isinjected into the floating gate FG1 from the first impurity diffusionregion IAa through the charge inlet 14 configured in the region wherethe tunnel insulating film is formed. Thus, the threshold voltage of thewriting element Mw33 becomes high. On the contrary, when the pulsevoltage Vpp is applied to the first impurity diffusion region IAa of thewriting element Mw33 and the low voltage Vss is applied to the controlgate CG1, an electron is emitted to the first impurity diffusion regionIAa from the floating gate FG1 through the charge inlet 14. Thus, thethreshold voltage of the writing element Mw33 becomes low. The controlgate CG1 and the floating gate FG1 are shared by the writing elementMw33, the driving element Mv33, and the dummy element Mm33. Therefore,the driving element Mv33 and the dummy element Mm33 each have the samethreshold voltage as that of the writing element Mw33.

It is a matter of course that the nonvolatile storage elements of thesame type are used as the MOSFETs configuring the reference voltagegeneration circuit RC3, i.e., transistor, in this embodiment. Therefore,in the reference voltage generation circuit RC3, the conductance or thetemperature characteristics can be made identical in the twotransistors, and thus the ideally translated characteristics of the twotransistors can be obtained.

FIG. 22 illustrates an example of the current/voltage characteristics ofa depression type transistor and an enhancement type transistor. Thehorizontal axis represents a gate-source voltage Vgs between the controlgate and the source region. The vertical axis represents a drain currentIds. “Md” represents the current/voltage characteristics of thedepression type transistor. “Me” represents the current/voltagecharacteristics of the enhancement type transistor. Since thegate-source voltage Vgs is fixed at 0 V, the depression type transistorMd passes a drain current of a constant current Iconst insofar as thedrain-source voltage between the drain region and the source region isin a saturated region. The drain current of the constant current Iconstflows also into the enhancement type transistor Me connected in seriesto the depression type transistor Md. Therefore, the gate-source voltageVgs of the enhancement type transistor Me in which Ids=Iconst isestablished can be extracted from the voltage output terminal OUT as thereference voltage Vref (i.e., a reference voltage VREF).

When the threshold voltage of the depression type transistor Md isexpressed as Vth_d and the threshold voltage of the enhancement typetransistor Me is expressed as Vth_e, the reference voltage Vref is thesum of the absolute value of the threshold voltage Vth_d and theabsolute value of the threshold voltage Vth_e, i.e., the referencevoltage Vref can be expressed as “Vref=|Vth_d|+|Vth_e|.

The translated current/voltage characteristics of the two transistorsillustrated in FIG. 22 cannot be strictly achieved because theconductance or the temperature characteristics varies/vary in eachtransistor when the depression type transistor and the enhancement typetransistor are configured using different types of transistors. Morespecifically, in a conventional reference voltage generation circuit,temperature characteristics arise also in a reference voltage extractedfrom a voltage output terminal. In contrast thereto, in the referencevoltage generation circuit in this embodiment using the nonvolatilestorage elements of the same type, the reference voltage Vref free frommanufacturing variations or temperature characteristics can be obtained.Moreover, it is one of advantages that the reference voltage Vref to beextracted can be set to an arbitrary value by adjusting the thresholdvoltage Vth_e of the enhancement type transistor. Furthermore, it isalso one of advantages that the amount of a current passed into thereference voltage generation circuit can be set to an arbitrary value byadjusting the threshold voltage Vth_d of the depression type transistor.

The reference voltage Vref can be adjusted by adjusting at least one ofthe threshold voltage Vth_d of the depression type transistor Md and thethreshold voltage Vth_e of the enhancement type transistor Me asappropriate. For example, when the threshold voltage Vth_d of thedepression type transistor Md is made high in a state where thethreshold voltage Vth_e of the enhancement type transistor Me is fixed,the current value of the constant current Iconst becomes large, andtherefore the reference voltage Vref also becomes high. For example,when the threshold voltage Vth_d of the depression type transistor Md ismade high in a state where the threshold voltage Vth_e of theenhancement type transistor Me is fixed, the current value of theconstant current Iconst becomes small, and therefore the referencevoltage Vref also becomes low. For example, when the threshold voltageVth_e of the enhancement type transistor Me is made low in a state wherethe threshold voltage Vth_d of the depression type transistor Md isfixed, the current value of the constant current Iconst does not varybut the reference voltage Vref becomes low. For example, when thethreshold voltage Vth_e of the enhancement type transistor Me is madehigh in a state where the threshold voltage Vth_d of the depression typetransistor Md is fixed, the current value of the constant current Iconstdoes not vary but the reference voltage Vref becomes high.

As described above, this embodiment can achieve a nonvolatile storageelement having high charge retention characteristics while givingflexibility to the layout of the elements. Therefore, a highly accurateanalog circuit can be achieved in which the degradation of electriccharacteristics is effectively suppressed and the influence ofmanufacturing variations is very low. Moreover, according to thisembodiment, variations in electric characteristics can be reduced. Anonvolatile storage element having excellent charge retentioncharacteristics and an analog circuit provided with the same can beachieved.

The reference voltage generation circuit RC3 in this embodiment has thenonvolatile storage element M1 of the configuration illustrated in FIGS.1 and 2A to 2C, and therefore a current path in the charge injection andthe charge emission and a current path during the operation of thereference voltage generation circuit RC3 (in driving of driving theother circuits) are separable. Thus, the reference voltage generationcircuit RC3 can prevent unexpected rewriting of the nonvolatile storageelement and can achieve an improvement of the reliability.

The nonvolatile storage element M1 according to this embodiment isprovided with the writing element Mw1 and the driving element Mv1 eachhaving the semiconductor substrate 9A, the floating gate FG1 providedabove the semiconductor substrate 9A, and the control gate CG2 disposedabove the floating gate FG1 to be insulated from the floating gate FG1.The writing element Mw1 is provided with the first impurity diffusionregion IAa provided in the semiconductor substrate 9A and partiallydisposed below the floating gate FG1 and the tunnel insulating film 25at least partially disposed between the floating gate FG1 and the firstimpurity diffusion region IAa and having an area ratio to the floatinggate FG1 of 0.002 or more and 1 or less. The driving element Mv1 isprovided with the drain region D1 provided in the semiconductorsubstrate 9A and formed to be electrically isolated from the firstimpurity diffusion region IAa and the source region S1 provided in thesemiconductor substrate 9A.

The nonvolatile storage element M1 having such a configuration cansuppress the first mode retention degradation and the second moderetention degradation.

The nonvolatile storage element M1 according to this embodiment isprovided with the floating gate FG1 having an area of 30 μm² or more.Thus, the nonvolatile storage element M1 according to this embodiment isusable as a MOSFET suitable for an analog circuit, such as a referencevoltage generating circuit. In the analog circuit provided with thenonvolatile storage element M1 according to this embodiment, acharacteristic fluctuation due to the retention degradation issuppressed and the influence of manufacturing variations or temperaturecharacteristics can be reduced. In the nonvolatile storage element M1,charge injection into to the floating gate FG1 or charge emission fromthe floating gate FG1 does not occur during the operation of the analogcircuit. This makes it easier for the nonvolatile storage element M1 tosuppress the characteristic fluctuation due to the retention degradationof the analog circuit.

Second Embodiment

A nonvolatile storage element according to a second embodiment of thepresent invention is described with reference to FIGS. 23A to 23C andFIGS. 24 to 26. First, the schematic configuration of a nonvolatilestorage element M2 according to this embodiment is described withreference to FIGS. 23A to 23C.

As illustrated in FIGS. 23A to 23C, the nonvolatile storage element M2according to this embodiment has a FLOTOX structure as with thenonvolatile storage element M1 according to the first embodiment. Thenonvolatile storage element M2 according to this embodiment is notlimited to the FLOTOX type and may have the other structures insofar asthe nonvolatile storage element M2 is an active element (transistor)having a charge retention region. The nonvolatile storage element M2 iselement-isolated by an element isolation region 42 formed in a P-typesemiconductor substrate 9B, for example, from another nonvolatilestorage element (not illustrated) formed on the same semiconductorsubstrate 9B. The nonvolatile storage element M2 is provided with awriting element Mw2 and a driving element (an example of the drivingMOSFET) Mv2 formed on the same semiconductor substrate 9B. Asillustrated in FIG. 23A, the writing element Mw2 and the driving elementMv2 are disposed adjacent to each other.

As illustrated in FIG. 23B, the writing element Mw2 provided in thenonvolatile storage element M2 is provided with the semiconductorsubstrate 9B and a gate insulating film 26 w provided on thesemiconductor substrate 9B. In the semiconductor substrate 9B, a P-wellregion 10B is formed. The gate insulating film 26 w is made of silicondioxide (SiO₂) and is disposed on the P-well region 10B. The gateinsulating film 26 w may be made of silicon nitride (SiN) without beinglimited to the silicon dioxide.

The writing element Mw2 is provided with a floating gate FG2 providedabove the semiconductor substrate 9B. A part of the floating gate FG2 isdisposed on the gate insulating film 26 w. The floating gate FG2 is madeof polysilicon. The entire floating gate FG2 has an area of 30 μm² ormore and 27000 μm² or less in a plan view of the nonvolatile storageelement M2 illustrated in FIG. 23A. Herein, the “entire floating gateFG2” means the floating gate provided in one nonvolatile storage elementM2 and does not mean the floating gate in predetermined portions, suchas a portion where the writing element Mw2 is provided and a portionwhere the driving element Mv2 is provided. Therefore, the “entirefloating gate FG2” is distinguished from a “specific region PA of thefloating FG12” (details are described later) in the portion where thedriving element Mv2 is provided. Hereinafter, the “floating gate FG2”means the “entire floating gate FG2” unless otherwise specified as the“specific region PA of the floating gate FG2”. The lower limit value ofthe area of the floating gate FG2 is specified for differentiation froma case where a nonvolatile storage element is used as a memory storingdigital data. The area of the floating gate FG2 in this embodiment is590 μm², for example, in the plan view of the nonvolatile storageelement M2. Herein, the plan view refers to a state where the plane(element formation surface) of the semiconductor substrate 9B on whichthe gate insulating film 26 w, the floating gate FG2, and the like areformed is viewed in an orthogonal direction to element formationsurface. The floating gate FG2 in this embodiment has an L shape in theplan view of the nonvolatile storage element M2 but may have the othershapes without being limited to the L shape.

The writing element Mw2 is provided with a control gate CG2 which isdisposed above the floating gate FG2 to be insulated from the floatinggate FG2. The control gate CG2 is made of polysilicon, for example. Thecontrol gate CG2 has an area smaller than that of the floating gate FG2in the plan view of the nonvolatile storage element M2. Although thecontrol gate CG2 has the same shape as that of the floating gate FG2 andhas a shape in which the size is one size smaller than that thereof inthe plan view of the nonvolatile storage element M2, the control gateCG2 may have the other shapes insofar as at least part thereof isdisposed on the floating gate FG2. For example, the control gate CG2 mayhave a shape projecting outward from the floating gate FG2 in the planview of the nonvolatile storage element M2. At this time, a contact plug(details are described later) for applying a voltage to the control gateCG2 may be formed in a partial region of the control gate CG2 projectingoutward from the floating gate FG2.

The writing element Mw2 is provided with an impurity diffusion region(an example of the first region) IA provided in the semiconductorsubstrate 9B and partially disposed in a part below the floating gateFG2. The impurity diffusion region IA is provided in the P-well region10B.

The impurity diffusion region IA has a diffusion layer 21 a, an N-typeLDD layer 22 a, and a contact layer 23 a having an impurityconcentration higher than that of the LDD layer 22 a. The contact layer23 a is provided in the LDD layer 22 a. The contact layer 23 a isprovided in order to take an ohmic contact between the impuritydiffusion region IA and a plug 53 a (details are described later). Theimpurity diffusion region IA is formed over a part below the floatinggate FG2 and a part of the side (one of both sides) of the floating gateFG2 in the plan view of the nonvolatile storage element M2 (see FIG.23A). The diffusion layer 21 a is provided in a part below the floatinggate FG2. The LDD layer 22 a and the contact layer 23 a are provided ina part of the side of the floating gate FG2.

The writing element Mw2 is provided with a tunnel insulating film 25 atleast partially disposed between the floating gate FG2 and the impuritydiffusion region IA and having an area ratio to the floating gate FG2 of0.002 or more and 1 or less. In this embodiment, the entire tunnelinsulating film 25 is disposed between the floating gate FG2 and thediffusion layer 21 a. The tunnel insulating film 25 is formed to besmaller than the floating gate FG2 in the plan view of the nonvolatilestorage element M2. The area of the tunnel insulating film 25 is 0.06μm² or more and 54 μm² or less in the plan view of the nonvolatilestorage element M2. The area of the tunnel insulating film 25 in thisembodiment is 25.2 μm², for example. Therefore, in this embodiment, theratio of the area of the tunnel insulating film 25 to the area of thefloating gate FG2 (area ratio), i.e., a value determined by dividing thearea of the tunnel insulating film 25 by the area of the floating gateFG2, is 0.043. Since the area ratio of the area the tunnel insulatingfilm 25 to the area (for example, 590 μm²) of the floating gate FG2 is0.043, which is larger than 0.002, the nonvolatile storage element M2can improve the first mode retention degradation as described in thefirst embodiment.

In order to perform writing of injecting a charge into the floating gateFG2 or extracting a charge from the floating gate FG2 by FN tunneling,the tunnel insulating film 25 is formed to have a thickness of 7 nm ormore and 12 nm or less. In this embodiment, the film thickness of thetunnel insulating film 25 is 9.8 nm, for example. When the filmthickness of the tunnel insulating film 25 is 7 to 12 nm, directtunneling of a charge becomes more unlikely to occur and a charge ismore easily retained in the floating gate FG2 as compared with the casewhere the film thickness is less than 7 nm. On the other hand, when thefilm thickness of the tunnel insulating film 25 is 7 to 12 nm, theinjection of a charge into the floating gate FG2 and the extraction of acharge from the floating gate FG2 can be accelerated as compared withthe case where the film thickness is larger than 12 nm. The tunnelinsulating film 25 is formed to have a film thickness smaller than thatof the gate insulating film 26 w. A region of the floating gate FG2corresponding to the tunnel insulating film 25 serves as a charge inlet24 injecting a charge into the floating gate FG2 or emitting a chargefrom the floating gate FG2. More specifically, the floating gate FG2 hasthe charge inlet 24 for injecting a charge or emitting a charge andfunctions as a charge retention region.

As illustrated in FIG. 23C, the driving element Mv2 provided in thenonvolatile storage element M2 is provided with the semiconductorsubstrate 9B and a gate insulating film 26 v provided on thesemiconductor substrate 9B. In this embodiment, the gate insulating film26 v of the driving element Mv2 is formed to be isolated from the gateinsulating film 26 w of the writing element Mw2 by the element isolationregion 42. The gate insulating film 26 v of the driving element Mv2 andthe gate insulating film 26 w of the writing element Mw2 may becontinuously formed and shared. The gate insulating film 26 v and thegate insulating film 26 w are simultaneously formed of the same materialin the same manufacturing process in the formation regions of thedriving element Mv2 and the writing element Mw2.

The driving element Mv2 is provided with the floating gate FG2 disposedon the gate insulating film 26 v. As with the gate insulating film 26 v,the floating gate FG2 is formed continuously formed in and shared by thedriving element Mv2 and the writing element Mw2. However, the floatinggate FG2 may be isolated in the driving element Mv2 and the writingelement Mw2. When the floating gate is isolated, the floating gate ofthe driving element Mv2 and the floating gate of the writing element Mw2need to be electrically connected by a plug and a metal wiring line, forexample, because the same voltage is applied thereto. The floating gateFG2 is simultaneously formed of the same material in the samemanufacturing process in the formation regions of the driving elementMv2 and the writing element Mw2.

The gate insulating film 26 v in the driving element Mv2 is disposedbetween the floating gate FG2 and the semiconductor substrate 9B in theportion where the driving element Mv2 is provided (i.e., specific regionPA) and has a film thickness larger than that of the tunnel insulatingfilm 25. The gate insulating film 26 v in the driving element Mv2 has analmost constant film thickness. No tunnel insulating film is provided inthe region where the gate insulating film 26 v is formed in the drivingelement Mv2. Therefore, the surface where the gate insulating film 26 vcontacts the floating gate FG2 in the driving element Mv2 has a flatshape.

The tunnel insulating film 25 in this embodiment is formed in an openingportion in which an insulating film for forming the gate insulating film26 w is opened as with the tunnel insulating film 25 in the firstembodiment. Therefore, the gate insulating film 26 w in the writingelement Mw2 has a level difference due to an opening portion in theregion where the tunnel insulating film 25 is provided. Therefore, thecontact surface with the floating gate FG2 is flatter in the gateinsulating film 26 v in the driving element Mv2 than in the gateinsulating film 26 w in the writing element Mw2.

The driving element Mv2 is provided with a source region S2 provided inthe semiconductor substrate 9B and a drain region (an example of thesecond region) D2 provided in the semiconductor substrate 9B and formedto be electrically isolated from the impurity diffusion region IA. Thesource region S2 and the drain region D2 are provided in the P-wellregion 10B. The drain region D2 and the source region S2 are defined bya current flowing direction. Therefore, when a direction of passing acurrent is reversed to a direction of passing a current assumed in thedriving element Mv2 illustrated in FIGS. 23A to 23C, the drain region D2illustrated in FIGS. 23A to 23C serves as the source region S2 and thesource region S2 serves as the drain region D2.

The source region S2 is provided in a part of the side (one of bothsides) of the floating gate FG2 in the plan view of the nonvolatilestorage element M2 (see FIG. 23A). The source region S2 has an N-typeLDD layer 22 s and a source layer 23 s having an impurity concentrationhigher than that of the LDD layer 22 s. The source layer 23 s isprovided in the LDD layer 22 s. The source layer 23 s is provided inorder to take an ohmic contact between the source region S2 and a plug53 s (details are described later).

The drain region D2 has an N-type LDD layer 22 d and a drain layer 23 dhaving an impurity concentration higher than that of the LDD layer 22 d.The drain layer 23 d is provided in the LDD layer 22 d. The drain layer23 d is provided in order to take an ohmic contact between the drainregion D2 and a plug 53 d (details are described later). The drainregion D2 is provided in a part of the side (the other side of bothsides) of the floating gate FG2 in the plan view of the nonvolatilestorage element M2 (see FIG. 23A). The source region S2 and the drainregion D2 are provided with the floating gate FG2 interposedtherebetween in the plan view of the nonvolatile storage element M2.

As illustrated in FIGS. 23B and 23C, the nonvolatile storage element M2is provided with an insulating film 27 disposed on the floating gate FG2and a sidewall 28 formed around the insulating film 27. The control gateCG2 is formed on the insulating film 27. The floating gate FG2 and thecontrol gate CG2 are insulated by the insulating film 27. The insulatingfilm 27 is configured combining a silicon oxide film and a siliconnitride film and has an oxide/nitride/oxide (ONO) structure. Theinsulating film 27 is provided covering the upper surface and the sidesurface of the floating gate FG2 and the side surfaces of the gateinsulating films 26 w and 26 v. The insulating film 27 and the sidewall28 are continuously formed in and shared by the driving element Mv2 andthe writing element Mw2. However, at least one of the insulating film 27and the sidewall 28 may be isolated in the driving element Mv2 and thewriting element Mw2. The insulating film 27 and the sidewall 28 each aresimultaneously formed of the same material in the same manufacturingprocess in the formation regions of the driving element Mv2 and thewriting element Mw2.

The insulating film 27 is disposed covering the floating gate FG2 overthe writing element Mw2 and the driving element Mv2. The sidewall 28 isdisposed surrounding the insulating film 27 in a level differenceportion of the lateral wall of the insulating film 27 over the writingelement Mw2 and the driving element Mv2. Therefore, the writing elementMw2 and the driving element Mv2 each have the insulating film 27 and thesidewall 28.

The nonvolatile storage element M2 has halogen (for example, fluorine)distributing in at least part of the gate insulating films 26 w and 26v, the tunnel insulating film 25, and the insulating film 27. In thisembodiment, halogen is contained in all of the gate insulating films 26w and 26 v, the tunnel insulating film 25, and the insulating film 27.Due to the fact that the tunnel insulating film 25 contains halogen (forexample, fluorine), the defect density of the tunnel insulating film 25decreases.

The nonvolatile storage element M2 is provided with the control gate CG2disposed on the insulating film 27 and a sidewall 29 formed around thecontrol gate CG2. The control gate CG2 and the sidewall 29 arecontinuously formed in and shared by the driving element Mv2 and thewriting element Mw2. However, at least one of the control gate CG2 andthe sidewall 29 may be isolated in the driving element Mv2 and thewriting element Mw2. When the control gate is isolated, the control gateof the driving element Mv2 and the control gate of the writing elementMw2 need to be electrically connected by a plug and a metal wiring line,for example, because the same voltage is applied thereto. The controlgate CG2 and the sidewall 29 each are simultaneously formed of the samematerial in the same manufacturing process in the formation regions ofthe driving element Mv2 and the writing element Mw2.

The nonvolatile storage element M2 is provided with an interlayerinsulating film 62 formed on the element formation surface of thesemiconductor substrate 9B. The interlayer insulating film 62 is formedat least in regions where the control gate CG2, the insulating film 27,the sidewalls 28 and 29, the source region S2, the drain region D2, andthe element isolation region 42 are provided. The interlayer insulatingfilm 62 is continuously formed in and shared by the driving element Mv2and the writing element Mw2. The interlayer insulating film 62 exhibitsthe function as a protective film protecting the control gate CG2, theimpurity diffusion region IA, the drain region D2, the source region S2,and the like.

The nonvolatile storage element M2 is provided with a plug 53 g embeddedin an opening portion exposing a part of the control gate CG2 to thebottom surface and formed in the interlayer insulating film 62 and ametal wiring line 54 g electrically connected to the plug 53 g andformed on the interlayer insulating film 62. The metal wiring line 54 gand the control gate CG2 are electrically connected through the plug 53g. This makes it possible to apply a voltage of a predetermined level tothe control gate CG2 from the metal wiring line 54 g through the plug 53g.

The driving element Mv2 is provided with a plug 53 s embedded in anopening portion exposing a part of the source layer 23 s to the bottomsurface and formed in the interlayer insulating film 62 and a metalwiring line 54 s electrically connected to the plug 53 s and formed onthe interlayer insulating film 62. The metal wiring line 54 s and thesource region S2 are electrically connected through the plug 53 s. Thismakes it possible to apply a voltage of a predetermined level to thesource region S2 from the metal wiring line 54 s through the plug 53 s.

The driving element Mv2 is provided with a plug 53 d embedded in anopening portion exposing a part of the second drain layer 73 d to thebottom surface and formed in the interlayer insulating film 62 and ametal wiring line 54 d electrically connected to the plug 53 d andformed on the interlayer insulating film 62. The metal wiring line 54 dand the drain region D2 are electrically connected through the plug 53d. This makes it possible to apply a voltage of a predetermined level tothe drain region D2 from the metal wiring line 54 d through the plug 53d.

The writing element Mw2 is provided with a plug 53 a embedded in anopening portion exposing a part of the contact layer 23 a to the bottomsurface and formed in the interlayer insulating film 62 and a metalwiring line 54 a electrically connected to the plug 53 a and formed onthe interlayer insulating film 62. The metal wiring line 54 a and theimpurity diffusion region IA are electrically connected through the plug53 a. This makes it possible to apply a voltage of a predetermined levelto the impurity diffusion region IA from the metal wiring line 54 athrough the plug 53 a.

As illustrated in FIG. 23C, the driving element Mv2 configures a MOSFET.The nonvolatile storage element M2 is configured to operate with theother circuits by causing the driving element Mv2 to function as aMOSFET. More specifically, a current path is formed in the drain regionD2 and the source region S2 of the driving element Mv2 when thenonvolatile storage element M2 operates with the other circuits. On theother hand, as illustrated in FIG. 23B, the impurity diffusion region IAis in a floating state and the writing element Mw2 does not configure aMOSFET. The writing element Mw2 functions as a voltage applicationelement in writing of injecting a charge into the floating gate FG2 oremitting a charge from the floating gate FG2. More specifically, theimpurity diffusion region IA functions as a writing voltage applicationregion and the drain region D2 functions as a drain region of thedriving MOSFET.

The FLOTOX nonvolatile storage element M2 according to this embodimentis used as the MOSFET in an analog circuit having an area of thefloating gate FG2 of 30 μm² or more as with the nonvolatile storageelement M1 according to the first embodiment. In this case, by settingthe area of the tunnel insulating film 25 to 50 μm² or less, theprobability that a charge in the floating gate FG2 excited by thermalenergy jumps over the energy barrier of the tunnel insulating film 25and leaks is suppressed and the nonvolatile storage element M2 cansuppress the second mode retention degradation. Moreover, by setting thearea ratio of the tunnel insulating film 25 to the floating gate FG2 to0.002 or more, the amount of charges passing through the tunnelinsulating film 25 per unit area thereof is suppressed and thenonvolatile storage element M2 can also suppress the first moderetention degradation. This makes it possible for the nonvolatilestorage element M2 to minimize the influence on analog circuitcharacteristics caused by the first mode retention degradation and thesecond mode retention degradation.

The nonvolatile storage element M2 according to this embodiment isprovided with the writing element Mw2 having the diffusion layer 21 adisposed below the tunnel insulating film 25 and the driving element Mv2configuring a MOSFET not having a tunnel insulating film between thefloating gate FG2 shared by the writing element Mw2 and the drain regionD2. The impurity diffusion region IA having the diffusion layer 21 a andthe drain region D2 are electrically isolated. Thus, while driving thedriving element Mv2, an excessive voltage or current is not generated inthe tunnel insulating film 25 through the impurity diffusion region IA.Therefore, charge injection into the floating gate FG2 through thetunnel insulating film 25 due to an electric field during the operationin which the nonvolatile storage element M2 drives the other circuits orinjection of a hot carrier generated by a current into the floating gateFG2 does not occur. As a result, the nonvolatile storage element M2 issuitable for the use as a more reliable MOSFET in an analog circuit.

The specific region PA which is a region of the floating gate FG2 in theportion where the driving element Mv2 is provided may have an area of17.5 μm² or more, for example. When the gate width of the specificregion PA of the floating gate FG2 is defined as W and the gate lengthof the specific region PA of the floating gate FG2 is defined as L (seeFIG. 23A), the gate width W and the gate length L of the specific regionPA of the floating gate FG2 may satisfy the relationship of Expression(4) described above. When the floating gate FG2 has an area larger than30 μm², the specific region PA of the floating gate FG2 may have an areaof 30 μm² or more. Thus, the nonvolatile storage element M2 according tothis embodiment obtains the same effects as those of the nonvolatilestorage element M1 according to the first embodiment.

Next, a method for adjusting the threshold voltage Vth of thenonvolatile storage element M2 is described.

For example, when 19 V is applied to the control gate CG2 and 0 V isapplied to the impurity diffusion region IA, an electron is injectedinto the floating gate FG2 through the tunnel insulating film 25, andthen the floating gate FG2 is brought into a negatively charged state.In this state, the floating gate FG2 acts in a direction of suppressingan electric field applied to the gate insulating film 26 v when apositive bias is applied to the control gate CG2. Therefore, thethreshold voltage Vth increases in the driving element Mv2 of thenonvolatile storage element M2 and the driving element Mv2 functions asenhancement type MOSFETs.

On the other hand, when 0 V is applied to the control gate CG2 and 19 Vis applied to the drain region D2, for example, an electron is extractedfrom the floating gate FG2 through the tunnel insulating film 25, andthen the floating gate FG2 is brought into a positively charged state.In this state, the floating gate FG2 acts in a direction of intensifyingan electric field applied to the gate insulating films 26 v when apositive bias is applied to the control gate CG2. Therefore, thethreshold voltage Vth decreases in the driving element Mv2 of thenonvolatile storage element M2 and the driving element Mv2 functions asa depression type MOSFET. Thus, the threshold voltage Vth of thenonvolatile storage element M2 can be adjusted to a desired value bycontrolling the injection of a charge into the floating gate FG2 or theextraction of a charge from the floating gate FG2.

A description of a method for manufacturing the nonvolatile storageelement M2 according to this embodiment is omitted because the shape ofa resist mask for forming the impurity diffusion region IA, the gateinsulating film 26 w, the tunnel insulating film 25, and the like isdifferent from that of the nonvolatile storage element M1 according tothe first embodiment but the formation material and the formation orderof each film are the same as that of the nonvolatile storage element M1according to the first embodiment.

(Reference Voltage Generation Circuit Provided with Nonvolatile StorageElement)

Next, a reference voltage generation circuit is described with referenceto FIGS. 24 to 26 as an example of the analog circuit provided with thenonvolatile storage element M2 according to this embodiment. The analogcircuit to which the nonvolatile storage element M2 is applied is notlimited to the reference voltage generation circuit insofar as thecircuit is a circuit using the nonvolatile storage element M2 in ananalog manner. For example, the nonvolatile storage element M2 iseffective also in analog circuits requiring accuracy in the thresholdvoltage of the MOSFET, such as an operational amplifier circuit and acomparator circuit.

As illustrated in FIG. 24, the reference voltage generation circuit RC2in this embodiment is provided with a nonvolatile storage element M21and a nonvolatile storage element M22 connected in series. Thenonvolatile storage element M21 and the nonvolatile storage element M22each have the same configuration as that of the nonvolatile storageelement M2 according to this embodiment illustrated in FIGS. 23A to 23C.The nonvolatile storage element M21 is provided with a writing elementMw21 and a driving element Mv21. The nonvolatile storage element M22 isprovided with a writing element Mw22 and a driving element Mv22. Thewriting element Mw21 and the writing element Mw22 have the sameconfiguration as that of the writing element Mw2 illustrated in FIG.23B. The driving element Mv21 and the driving element Mv22 have the sameconfiguration as that of the driving element Mv2 illustrated in FIG.23C.

The control gate CG2 of the driving element Mv21 and the control gateCG2 of the writing element Mw21 are shared. The floating gate FG2 of thedriving element Mv21 and the floating gate FG2 of the writing elementMw21 are shared. The charge inlet 24 (see FIGS. 23A and 23B) provided inthe writing element Mw21 is formed in a region not in contact with acurrent path formed in the driving element Mv21. The charge inlet 24provided in the writing element Mw21 is formed in a region not incontact with a current path including the drain region D2 and the sourceregion S2 of the driving element Mv21.

The control gate CG2 of the driving element Mv22 and the control gateCG2 of the writing element Mw22 are shared. The floating gate FG2 of thedriving element Mv22 and the floating gate FG2 of the writing elementMw22 are shared. The charge inlet 24 (see FIGS. 23A and 23B) provided inthe writing element Mw22 is formed in a region not in contact with acurrent path formed in the driving element Mv22. The charge inlet 24provided in the writing element Mw22 is formed in a region not incontact with a current path including the drain region D2 and the sourceregion S2 of the driving element Mv22.

The driving element Mv21 and the driving element Mv22 are connected inseries between a high voltage supply terminal Vdd and a low voltagesupply terminal Vss. Hereinafter, the mark “Vdd” is used also as themark of a high voltage output from the high voltage supply terminal Vdd.More specifically, the drain region D2 of the driving element Mv21 isconnected to the high voltage supply terminal Vdd. The source region S2of the driving element Mv22 is connected to the low voltage supplyterminal Vss. The source region S2 of the driving element Mv21 and thedrain region D2 of the driving element Mv22 are connected.

The writing element Mw21 is provided with the impurity diffusion regionIA partially disposed below the floating gate FG2. The reference voltagegeneration circuit RC2 is provided with a switch SW21 having oneterminal connected to the impurity diffusion region IA of the writingelement Mw21. One of the other terminals of the switch SW21 is connectedto a low voltage supply terminal Vss and the other one of the otherterminals of the switch SW21 is connected to an application terminal ofa pulse voltage Vpp. The reference voltage generation circuit RC2 isconfigured to be able to apply either one of the low voltage Vss and thepulse voltage Vpp to the impurity diffusion region IA of the writingelement Mw21 by switching the switch SW21 as appropriate.

The writing element Mw22 is provided with the impurity diffusion regionIA partially disposed below the floating gate FG2. The reference voltagegeneration circuit RC2 is provided with a switch SW22 having oneterminal connected to the impurity diffusion region IA of the writingelement Mw22. One of the other terminals of the switch SW22 is connectedto the low voltage supply terminal Vss and the other one of the otherterminals of the switch SW22 is connected to an application terminal ofthe pulse voltage Vpp. The reference voltage generation circuit RC2 isconfigured to be able to apply either one of the low voltage Vss and thepulse voltage Vpp to the impurity diffusion region IA of the writingelement Mw22 by switching the switch SW22 as appropriate.

The reference voltage generation circuit RC2 is provided with a switchSW25 and a switch SW27 connected in series between the control gate CG2of the writing element Mw21 and the control gate CG2 of the writingelement Mw22. The other terminals of the switch SW25 and the switch SW27are connected to each other. The other terminals of the switch SW25 andthe switch SW27 are connected to a connection portion where the sourceregion S2 of the driving element Mv21 and the drain region D2 of thedriving element Mv22 are connected to each other. The reference voltagegeneration circuit RC2 is provided with a voltage output terminal OUTconnected to the connection portion and outputting the reference voltageVref.

The reference voltage generation circuit RC2 is provided with a switchSW23 having one terminal connected to the control gate CG2 of thewriting element Mw21 and a switch SW29 having one terminal connected tothe other terminal of the switch SW23. One of the other terminals of theswitch SW29 is connected to an application terminal of a pulse voltageVpp and the other one of the other terminals of the switch SW29 isconnected to a low voltage supply terminal Vss. The reference voltagegeneration circuit RC2 is configured to be able to apply either one ofthe pulse voltage Vpp and the low voltage Vss to the control gate CG2 ofthe writing element Mw21 by switching the switch SW29 as appropriatewhen the switch SW23 is in a connection state (short-circuit state).

The reference voltage generation circuit RC2 is provided with a switchSW24 having one terminal connected to the control gate CG2 of thewriting element Mw22 and a switch SW20 having one terminal connected tothe other terminal of the switch SW24. One of the other terminals of theswitch SW20 is connected to an application terminal of a pulse voltageVpp and the other one of the other terminals of the switch SW20 isconnected to a low voltage supply terminal Vss. The reference voltagegeneration circuit RC2 is configured to be able to apply either one ofthe pulse voltage Vpp and the low voltage Vss to the control gate CG2 ofthe writing element Mw22 by switching the switch SW20 as appropriatewhen the switch SW24 is in a connection state (short-circuit state).

The writing element Mw21 is a region present for injecting a charge intothe floating gate FG2 of the driving element Mv21 and does not pass acurrent as a transistor. Similarly, the writing element Mw22 is a regionpresent for injecting a charge into the floating gate FG2 of the drivingelement Mv22 and does not pass a current as a transistor. Therefore, thewriting element Mw21 and the writing element Mw22 need not to have asource region or a drain region and the form is not limited insofar as astructure of having a charge inlet is provided.

As illustrated in FIG. 24, a charge is injected into the floating gateFG2 through the writing elements Mw21 and Mw22 in the charge injectionin the reference voltage generation circuit RC2. When operating thereference voltage generation circuit RC2, a current flows through thedriving elements Mv21 and Mv22. In the reference voltage generationcircuit RC2, the nonvolatile storage element M21 side (i.e., writingelement Mw21 and driving element Mv21) is in a depression state and thenonvolatile storage element M22 side (i.e., writing element Mw22 anddriving element Mv22) is in an enhancement state.

As illustrated in FIG. 24, the reference voltage generation circuit RC2switches the switches SW20 to SW25, SW27, and SW29 to the followingstates when generating the reference voltage Vref (i.e., when thereference voltage generation circuit RC2 operates).

Switch SW20: Arbitrary (low voltage supply terminal Vss side in FIG. 24)

Switch SW21: Low voltage supply terminal Vss side

Switch SW22: Low voltage supply terminal Vss side

Switches SW23 and SW24: Open state (open-circuit state)

Switch SW25, SW27: Connection state (short-circuit state)

Switch SW29: Arbitrary (low voltage supply terminal Vss side in FIG. 24)

As illustrated in FIG. 25, the reference voltage generation circuit RC2switches the switches SW20 to SW25, SW27, and SW29 to the followingstates in rewriting for bringing the nonvolatile storage element M21side (i.e., writing element Mw21 and driving element Mv21) into adepression state. Herein, a case where the threshold voltage before theadjustment on the nonvolatile storage element M21 side is higher thanthe threshold voltage after the adjustment is taken as an example.

Switch SW20: Arbitrary (low voltage supply terminal Vss side in FIG. 25)

Switch SW21: Pulse voltage Vpp side

Switch SW22: Low voltage supply terminal Vss side

Switch SW23: Connection state (short-circuit state)

Switch SW24: Open state (open-circuit state)

Switches SW25 and SW27: Open-circuit state

Switch SW29: Low voltage supply terminal Vss side

Therefore, the pulse voltage Vpp is applied to the impurity diffusionregion IA of the writing element Mw21 and the low voltage Vss is appliedto the control gate CG2, and therefore an electron is emitted to thedrain region D2 from the floating gate FG2 through the charge inlet 24configured in a region where the tunnel insulating film is formed. Thus,the threshold voltage of the writing element Mw21 becomes low. On thecontrary, when the low voltage Vss is applied to the drain region D2 ofthe writing element Mw21 and the pulse voltage Vpp is applied to thecontrol gate CG2, an electron is injected into the floating gate FG2from the drain region D2 through the charge inlet 24. Thus, thethreshold voltage of the writing element Mw21 becomes high. The controlgate CG2 and the floating gate FG2 are shared by the writing elementMw21 and the driving element Mv21. Therefore, the driving element Mv21has the same threshold voltage as that of the writing element Mw21.

As illustrated in FIG. 26, the reference voltage generation circuit RC2switches the switches SW20 to SW25, SW27, and SW29 to the followingstates in rewriting for bringing the nonvolatile storage element M22side (i.e., writing element Mw22 and driving element Mv22) into anenhancement state. Herein, a case where the threshold voltage before theadjustment on the nonvolatile storage element M22 side is lower than thethreshold voltage after the adjustment is taken as an example.

Switch SW20: Pulse voltage Vpp side

Switch SW21: Low voltage supply terminal Vss side

Switch SW22: Low voltage supply terminal Vss side

Switch SW23: Open state (open-circuit state)

Switch SW24: Connection state (short-circuit state)

Switch SW25, SW27: Open state (open-circuit state)

Switch SW29: Arbitrary (low voltage supply terminal Vss side in FIG. 26)

Therefore, the low voltage Vss is applied to the impurity diffusionregion IA of the writing element Mw22 and the pulse voltage Vpp isapplied to the control gate CG2, and therefore an electron is injectedinto the floating gate FG2 from the impurity diffusion region IA throughthe charge inlet 24 configured in the region where the tunnel insulatingfilm is formed. Thus, the threshold voltage of the writing element Mw22becomes high. On the contrary, when the pulse voltage Vpp is applied tothe impurity diffusion region IA of the writing element Mw22 and the lowvoltage Vss is applied to the control gate CG2, an electron is emittedto the impurity diffusion region IA from the floating gate FG2 throughthe charge inlet 24. Thus, the threshold voltage of the writing elementMw22 becomes low. The control gate CG2 and the floating gate FG2 areshared by the writing element Mw22 and the driving element Mv22.Therefore, the driving element Mv22 has the same threshold voltage asthat of the writing element Mw22.

As described above, this embodiment can achieve a nonvolatile storageelement having high charge retention characteristics while givingflexibility to the layout of the elements. Therefore, a highly accurateanalog circuit in which the degradation of electric characteristics iseffectively suppressed and the influence of manufacturing variations isvery low can be achieved. Moreover, according to this embodiment,variations in electric characteristics can be reduced. A nonvolatilestorage element having excellent charge retention characteristics and ananalog circuit provided with the same can be achieved.

The nonvolatile storage element according to this embodiment and theanalog circuit provided with the same can adjust the threshold voltageby adjusting the amount of charges of the floating gates FG2 of thenonvolatile storage elements M21 and M22, and therefore the same effectsas those of the nonvolatile storage element according to the firstembodiment and the analog circuit provided with the same are obtained.

The reference voltage generation circuit RC2 in this embodiment isprovided with the nonvolatile storage element M2 of the configurationillustrated in FIGS. 23A to 23C, and therefore the current path in thecharge injection and the charge emission and the current path during theoperation of the reference voltage generation circuit RC2 (in driving ofdriving the other circuits) are separable. Thus, the reference voltagegeneration circuit RC2 can prevent unexpected rewriting of thenonvolatile storage element and can achieve an improvement of thereliability.

The nonvolatile storage element M2 according to this embodiment isprovided with the writing element Mw2 and the driving element Mv2 havingthe semiconductor substrate 9B, the floating gate FG2 provided above thesemiconductor substrate 9B, and the control gate CG2 disposed to beinsulated from the floating gate FG2. The writing element Mw2 isprovided with the impurity diffusion region IA provided in thesemiconductor substrate 9B and partially disposed below the floatinggate FG2 and the tunnel insulating film 25 at least partially disposedbetween the floating gate FG2 and the first impurity diffusion regionIAa and having an area ratio to the floating gate FG2 of 0.002 or moreand 1 or less. The driving element Mv2 is provided with the drain regionD2 provided in the semiconductor substrate 9A and formed to beelectrically isolated from the impurity diffusion region IA and thesource region S2 provided in the semiconductor substrate 9A.

The nonvolatile storage element M2 having such a configuration cansuppress the first mode retention degradation and the second moderetention degradation.

The nonvolatile storage element M2 according to this embodiment isprovided with the floating gate FG2 having an area of 30 μm² or more.Thus, the nonvolatile storage element M2 according to this embodiment isusable as a MOSFET suitable for an analog circuit, such as a referencevoltage generating circuit. In the analog circuit provided with thenonvolatile storage element M2 according to this embodiment, acharacteristic fluctuation due to the retention degradation issuppressed and the influence of manufacturing variations or temperaturecharacteristics can be reduced. Furthermore, in the nonvolatile storageelement M2, charge injection into to the floating gate FG2 or chargeemission from the floating gate FG2 does not occur during the operationof the analog circuit. This makes it easier for the nonvolatile storageelement M2 to suppress the characteristic fluctuation due to theretention degradation of the analog circuit.

Third Embodiment

A nonvolatile storage element according to a third embodiment of thepresent invention is described with reference to FIGS. 27A and 27B to31. First, the schematic configuration of the nonvolatile storageelement according to this embodiment is described with reference toFIGS. 27A and 27B.

As illustrated in FIG. 27A, a wiring element and a driving element arenot isolated and a writing operation and a driving operation areperformed by one element in a nonvolatile storage element M7 accordingto this embodiment unlike the nonvolatile storage elements M1 and M2according to the first and second embodiments, respectively. Asillustrated in FIG. 27B, the nonvolatile storage element M7 according tothis embodiment has a FLOTOX type structure as with the nonvolatilestorage element M1 according to the first embodiment. The nonvolatilestorage element M7 according to this embodiment is not limited to theFLOTOX type and may have the other structures insofar as the nonvolatilestorage element M7 is an active element (transistor) having a chargeretention region.

The nonvolatile storage element M7 according to this embodiment iselement-isolated by an element isolation region 43 formed in a P-typesemiconductor substrate 9C, for example, from another nonvolatilestorage element (not illustrated) formed on the same semiconductorsubstrate 9C.

As illustrated in FIG. 27B, the nonvolatile storage element M7 accordingto this embodiment is provided with the semiconductor substrate 9C and agate insulating film 76 provided on the semiconductor substrate 9C. AP-well region 10C is formed in the semiconductor substrate 9C. The gateinsulating film 76 is made of silicon dioxide (SiO₂) and is disposed onthe P-well region 10C. The gate insulating film 76 may be made ofsilicon nitride (SiN) without being limited to the silicon dioxide.

The nonvolatile storage element M7 is provided with a floating gate FG7provided above the semiconductor substrate 9C. A part of the floatinggate FG7 is disposed on the gate insulating film 76. The floating gateFG7 is made of polysilicon. The entire floating gate FG7 has an area of30 μm² or more and 27000 μm² or less in a plan view of the nonvolatilestorage element M7 illustrated in FIG. 27A. Herein, the “entire floatinggate FG7” means the floating gate provided in one nonvolatile storageelement M7. A region of the floating gate in portions functioning as awriting element and a driving element (i.e., specific region of thefloating gate) is formed to be smaller than the entire floating gateFG7. Therefore, the “entire floating gate FG7” is distinguished from the“specific region PA of the floating FG7” in the portions functioning asthe writing element and the driving element. Hereinafter, the “floatinggate FG7” means the “entire floating gate FG7” unless otherwisespecified as the “specific region PA of the floating gate FG7”. Thelower limit value of the area of the floating gate FG7 is specified fordifferentiation from a case where a nonvolatile storage element is usedas a memory storing digital data. The area of the floating gate FG7 inthis embodiment is 1422 μm², for example, in the plan view of thenonvolatile storage element M7. Herein, the plan view refers to a statewhere the plane (element formation surface) of the semiconductorsubstrate 9C on which the gate insulating film 76, the floating gateFG7, and the like are formed is viewed in an orthogonal direction to theelement formation surface. The floating gate FG7 in this embodiment hasa rectangular shape in the plan view of the nonvolatile storage elementM7 but may have the other shapes without being limited to therectangular shape.

The nonvolatile storage element M7 is provided with an insulating film77 disposed on the floating gate FG7 and a sidewall 78 formed around theinsulating film 77. The insulating film 77 is configured combining asilicon oxide film and a silicon nitride film and has anoxide/nitride/oxide (ONO) structure. The insulating film 77 is providedcovering the upper surface and the side surface of the floating gate FG7and the side surface of the gate insulating film 76.

The nonvolatile storage element M7 is provided with a control gate CG7disposed above the floating gate FG7 to be insulated from the floatinggate FG7 and a sidewall 79 formed around the control gate CG7. Thecontrol gate CG7 is made of polysilicon, for example. The control gateCG7 has an area smaller than that of the floating gate FG7 in the planview of the nonvolatile storage element M7 (see FIG. 27A). The controlgate CG7 has a rectangular shape in the plan view of the nonvolatilestorage element M7 but may have the other shapes insofar as the controlgate CG7 is disposed on the floating gate FG7 without being limited tothe rectangular shape. The control gate CG7 is disposed on theinsulating film 77. The control gate CG7 is insulated from the floatinggate FG7 by the insulating film 77.

The nonvolatile storage element M7 is provided with a source region S7provided in the semiconductor substrate 9C and a drain region (anexample of the first region) D7 provided in the semiconductor substrate9C and partially disposed below the floating gate FG7. The source regionS7 and the drain region D7 are provided in the P-well region 10C. Thedrain region D7 and the source region S7 are defined by a currentflowing direction. Therefore, when a direction of passing a current isreversed to a direction of passing a current assumed in the nonvolatilestorage element M7 illustrated in FIGS. 27A and 27B, the drain region D7illustrated in FIGS. 27A and 27B serves as the source region S7 and thesource region S7 serves as the drain region D7.

The source region S7 is provided in a part of the side (one of bothsides) of the floating gate FG7 in the plan view of the nonvolatilestorage element M7 (see FIG. 27A). The source region S7 has an N-typeLDD layer 72 s and a source layer 73 s having an impurity concentrationhigher than that of the LDD layer 72 s. The source layer 73 s isprovided in the LDD layer 72 s. The source layer 73 s is provided inorder to take an ohmic contact between the source region S7 and a plug55 s (details are described later).

The drain region D7 has a first drain layer 71 d, an N-type LDD layer 72d, and a second drain layer 73 d having an impurity concentration higherthan that of the LDD layer 72 d. The second drain layer 73 d is providedin the LDD layer 72 d. The drain layer 73 d is provided in order to takean ohmic contact between the drain region D7 and a plug 55 d (detailsare described later). The drain region D7 is provided over a part belowthe floating gate FG7 and the side (the other side of both sides) of thefloating gate FG7 in the plan view of the nonvolatile storage element M7(see FIG. 27A). The first drain layer 71 d is provided below thefloating gate FG7 and the LDD layer 72 d and the second drain layer 73 dare provided on the side of the floating gate FG7. The LDD layer 72 dand the LDD layer 72 s are provided with the floating gate FG7interposed therebetween in the plan view of the nonvolatile storageelement M7.

The nonvolatile storage element M7 is provided with a tunnel insulatingfilm 75 at least partially disposed between the floating gate FG7 andthe drain region D7 and having an area ratio to the floating gate FG7 of0.002 or more and 1 or less. In this embodiment, the entire tunnelinsulating film 75 is disposed between the floating gate FG7 and thefirst drain layer 71 d. The tunnel insulating film 75 is formed to besmaller than the floating gate FG7 in the plan view of the nonvolatilestorage element M7. The area of the tunnel insulating film 75 is 0.06μm² or more and 54 μm² or less in the plan view of the nonvolatilestorage element M7. When the area of the entire floating gate FG7 is 30μm² of the minimum value and the area ratio of the tunnel insulatingfilm 75 to the floating gate FG7 is 0.002 of the minimum value, the areaof the tunnel insulating film 75 is 0.06 μm² of the minimum value. Thearea of the tunnel insulating film 75 in this embodiment is 25 μm², forexample. Therefore, in this embodiment, the ratio of the area of thetunnel insulating film 75 to the area of the floating gate FG7 (arearatio), i.e., a value determined by dividing the area of the tunnelinsulating film 75 by the area of the floating gate FG7, is 0.017. Sincethe area ratio of the area of the tunnel insulating film 75 to the areaof the floating gate FG7 is 0.017, which is larger than 0.002, thenonvolatile storage element M7 can improve the first mode retentiondegradation as described in the first embodiment.

In order to perform writing of injecting a charge into the floating gateFG7 or extracting a charge from the floating gate FG7 by FN tunneling,the thickness of the tunnel insulating film 75 may be 7 nm or more and12 nm or less. In this embodiment, the film thickness of the tunnelinsulating film 75 is 9.8 nm, for example. When the film thickness ofthe tunnel insulating film 75 is 7 to 12 nm, direct tunneling of acharge becomes more unlikely to occur and a charge is more easilyretained in the floating gate FG7 as compared with the case where thefilm thickness is less than 7 nm. On the other hand, when the filmthickness of the tunnel insulating film 75 is 7 to 12 nm, the injectionof a charge into the floating gate FG7 and the extraction of a chargefrom the floating gate FG7 can be accelerated as compared with a casewhere the film thickness is larger than 12 nm. The tunnel insulatingfilm 75 may be formed to have a film thickness smaller than that of thegate insulating film 76. A region of the floating gate FG7 correspondingto the tunnel insulating film 75 serves as a charge inlet 74 injecting acharge into the floating gate FG7 or emitting a charge from the floatinggate FG7. More specifically, the floating gate FG7 has the charge inlet74 for injecting a charge or emitting a charge and functions as a chargeretention region.

The nonvolatile storage element M7 has halogen (for example, fluorine)distributing in at least part of the tunnel insulating film 75, the gateinsulating film 76, and the insulating film 77. In this embodiment,halogen is contained in all of the tunnel insulating film 75, the gateinsulating film 76, and the insulating film 77. Due to the fact that thetunnel insulating film 75 contains halogen (for example, fluorine), thedefect density of the tunnel insulating film 75 decreases.

The nonvolatile storage element M7 is provided with and an interlayerinsulating film 63 formed on the element formation surface of thesemiconductor substrate 9C. The interlayer insulating film 63 is formedat least in regions where the control gate CG7, the insulating film 77,the sidewalls 78 and 79, the drain region D7, the source region S7, andthe element isolation region 43 are provided. The interlayer insulatingfilm 63 exhibits the function as a protective film protecting thecontrol gate CG7, the drain region D7, the source region S7, and thelike.

The nonvolatile storage element M7 is provided with a plug 55 g embeddedin an opening portion exposing a part of the control gate CG7 to thebottom surface and formed in the interlayer insulating film 63 and ametal wiring line 56 g electrically connected to the plug 55 g andformed on the interlayer insulating film 63. The metal wiring line 56 gand the control gate CG7 are electrically connected through the plug 55g. This makes it possible to apply a voltage of a predetermined level tothe control gate CG7 from the metal wiring line 56 g through the plug 55g.

The nonvolatile storage element M7 is provided with a plug 55 d embeddedin an opening portion exposing a part of the second drain layer 73 d tothe bottom surface and formed in the interlayer insulating film 63 and ametal wiring line 56 d electrically connected to the plug 55 d andformed on the interlayer insulating film 63. The metal wiring line 56 dand the drain region D7 are electrically connected through the plug 55d. This makes it possible to apply a voltage of a predetermined level tothe drain region D7 from the metal wiring line 56 d through the plug 55d.

The nonvolatile storage element M7 is provided with a plug 55 s embeddedin an opening portion exposing a part of the source layer 73 s to thebottom surface and formed in the interlayer insulating film 63 and ametal wiring line 56 s electrically connected to the plug 55 s andformed on the interlayer insulating film 63. The metal wiring line 56 sand the source region S7 are electrically connected through the plug 55s. This makes it possible to apply a voltage of a predetermined level tothe source region S7 from the metal wiring line 56 s through the plug 55s.

The specific region PA of the floating gate FG7 may have an area of 17.5μm² or more, for example. When the gate width of the specific region PAof the floating gate FG7 is defined as W and the gate length of thespecific region PA of the floating gate FG7 is defined as L (see FIG.27A), the gate width W and the gate length L of the specific region PAof the floating gate FG7 may satisfy the relationship of Expression (4)described above. When the floating gate FG7 has an area larger than 30μm², the specific region PA of the floating gate FG7 may have an area of30 μm² or more. Thus, the nonvolatile storage element M7 according tothis embodiment obtains the same effects as those of the nonvolatilestorage element M1 according to the first embodiment.

Next, a method for adjusting the threshold voltage Vth of thenonvolatile storage element M7 is described.

For example, when 19 V is applied to the control gate CG7 and 0 V isapplied to the drain region D7, an electron is injected into thefloating gate FG7 through the tunnel insulating film 75, and then thefloating gate FG7 is brought into a negatively charged state. In thisstate, the floating gate FG7 acts in a direction of suppressing anelectric field applied to the gate insulating film 76 when a positivebias is applied to the control gate CG7. Therefore, the thresholdvoltage Vth increases in the nonvolatile storage element M7 and thenonvolatile storage element M7 functions as an enhancement type MOSFET.

On the other hand, when 0 V is applied to the control gate CG7 and 19 Vis applied to the drain region D7, for example, an electron is extractedfrom the floating gate FG7 through the tunnel insulating film 75, andthen the floating gate FG7 is brought into a positively charged state.In this state, the floating gate FG7 acts in a direction of intensifyingan electric field applied to the gate insulating films 76 when apositive bias is applied to the control gate CG7. Therefore, thethreshold voltage Vth decreases in the nonvolatile storage element M7and the nonvolatile storage element M7 functions as a depression typeMOSFET. Thus, the threshold voltage Vth of the nonvolatile storageelement M7 can be adjusted to a desired value by controlling theinjection of a charge into the floating gate FG7 or the extraction of acharge from the floating gate FG7.

(Reference Voltage Generation Circuit Provided with Nonvolatile StorageElement)

Next, a reference voltage generation circuit is described with referenceto FIGS. 28 to 31 as an example of the analog circuit provided with thenonvolatile storage element M7 according to this embodiment. The analogcircuit to which the nonvolatile storage element M7 is applied is notlimited to the reference voltage generation circuit insofar as thecircuit is a circuit using the nonvolatile storage element M7 in ananalog manner. For example, the nonvolatile storage element M7 iseffective also in analog circuits requiring accuracy in the thresholdvoltage of the MOSFET, such as an operational amplifier circuit and acomparator circuit.

As illustrated in FIG. 28, the reference voltage generation circuit RC6in this embodiment is provided with a plurality (two in this example) ofnonvolatile storage elements M71 and M72. At least some of the pluralityof nonvolatile storage elements M71 and M72 (both the nonvolatilestorage elements in this example) are connected in series and a voltageoutput terminal OUT outputting the reference voltage Vref is connectedto a connection portion of the plurality of nonvolatile storage elementsM71 and M72 connected in series. Both the nonvolatile storage elementM71 and the nonvolatile storage element M72 have the FLOTOX typeconfiguration of an N-type MOSFET and have the same configuration asthat of the nonvolatile storage element M7 illustrated in FIGS. 27A and27B.

The nonvolatile storage element M71 and the nonvolatile storage elementM72 are connected in series between a high voltage supply terminal Vddto which a high voltage is supplied and a low voltage supply terminalVss to which a low voltage is supplied. The drain region D7 of thenonvolatile storage element M71 is connected to the high voltage supplyterminal Vdd. A source region S7 of the nonvolatile storage element M72is connected to the low voltage supply terminal Vss. The source regionS7 and the control gate CG7 of the nonvolatile storage element M71 areconnected to each other. The drain region D7 and the control gate CG7 ofthe nonvolatile storage element M72 are connected to each other. Thesource region S7 and the control gate CG7 of the nonvolatile storageelement M71 and the drain region D7 and the control gate CG7 of thenonvolatile storage element M72 are connected to each other. The voltageoutput terminal OUT is connected to a connection portion of the sourceregion S7 of the nonvolatile storage element M71 and the drain region D7of the nonvolatile storage element M72.

In the reference voltage generation circuit RC6, the nonvolatile storageelement M72 on the lower stage side (low voltage supply terminal Vssside) is adjusted to be brought into an enhancement state and thenonvolatile storage element M71 on the upper stage side (high voltagesupply terminal Vdd side) is adjusted to be brought into a depressionstate. The nonvolatile storage elements M71 and M72 each have thecontrol gate CG7 and the floating gate FG7, in which fluorine isdistributed as halogen in the tunnel insulating film 75, the gateinsulating film 76, and the insulating film 77 (see FIG. 27B) around thefloating gate FG7. Thus, the nonvolatile storage elements M71 and M72can perform writing/erasing and can hold a writing state over a longperiod of time. The threshold voltage of a depression type transistorbecomes negative and the threshold voltage of an enhancement typetransistor becomes positive. Therefore, the plurality of nonvolatilestorage elements provided in the reference voltage generation circuitRC6 as the analog circuit according to this embodiment contain at leastthe nonvolatile storage element M71 having a negative threshold voltageand the nonvolatile storage element M72 having a positive thresholdvoltage. The nonvolatile storage elements M71 and M72 do not have anarray structure.

As illustrated in FIG. 29, a reference voltage generation circuit RC7which is the analog circuit according to this embodiment and which canperform writing in the nonvolatile storage elements M71 and M72 isprovided with a switch SW71 having one terminal connected to the drainregion D7 of the nonvolatile storage element M71. One of the otherterminals of the switch SW71 is connected to a high voltage supplyterminal Vdd, another of the other terminals of the switch SW71 isconnected to a low voltage supply terminal Vss, and the other one of theother terminals of the switch SW71 is connected to an applicationterminal of a pulse voltage Vpp. The reference voltage generationcircuit RC7 is configured to be able to apply either one of the highvoltage Vdd, the low voltage Vss, and the pulse voltage Vpp to the drainregion D7 of the nonvolatile storage element M71 by switching the switchSW71 as appropriate.

The reference voltage generation circuit RC7 is provided with a switchSW72 having one terminal connected to the source region S7 of thenonvolatile storage element M72. One of the other terminals of theswitch SW72 is connected to a low voltage supply terminal Vss and theother one of the other terminals of the switch SW72 is connected to anapplication terminal of a pulse voltage Vpp. The reference voltagegeneration circuit RC7 is configured to be able to apply either one ofthe low voltage Vss and the pulse voltage Vpp to the source region S7 ofthe nonvolatile storage element M72 by switching the switch SW72 asappropriate.

The reference voltage generation circuit RC7 is provided with a switchSW76 and a switch SW78 connected in series between the source region S7of the nonvolatile storage element M71 and the drain region D7 of thenonvolatile storage element M72. The source region S7 of the nonvolatilestorage element M71 is connected to one terminal of the switch SW76 andthe drain region D7 of the nonvolatile storage element M72 is connectedto one terminal of the switch SW78. The other terminal of the switchSW76 and the other terminal of the switch SW78 are connected.

The reference voltage generation circuit RC7 is provided with a switchSW75 and a switch SW77 connected in series between the control gate CG7of the nonvolatile storage element M71 and the control gate CG7 of thenonvolatile storage element M72. The control gate CG7 of the nonvolatilestorage element M71 is connected to one terminal of the switch SW75 andthe control gate CG7 of the nonvolatile storage element M72 is connectedto one terminal of the switch SW77. The other terminal of the switchSW75 and the other terminal of the switch SW77 are connected.

The other terminals of the switch SW75, the switch SW76, the switchSW77, and the switch SW78 are connected to each other. The referencevoltage generation circuit RC7 is provided with the voltage outputterminal OUT connected to a connection portion where the other terminalsof the switch SW75, the switch SW76, the switch SW77, and the switchSW78 are connected to each other.

The reference voltage generation circuit RC7 is provided with a switchSW73 having one terminal connected to the control gate CG7 of thenonvolatile storage element M71 and a switch SW79 having one terminalconnected to the other terminal of the switch SW73. One of the otherterminals of the switch SW79 is connected to an application terminal ofa pulse voltage Vpp and the other one of the other terminals of theswitch SW79 is connected to a low voltage supply terminal Vss. Thereference voltage generation circuit RC7 is configured to be able toapply either one of the pulse voltage Vpp and the low voltage Vss to thecontrol gate CG7 of the nonvolatile storage element M71 by switching theswitch SW79 as appropriate when the switch SW73 is in a connection state(short-circuit state).

The reference voltage generation circuit RC7 is provided with a switchSW74 having one terminal connected to the control gate CG7 of thenonvolatile storage element M72 and a switch SW70 having one terminalconnected to the other terminal of the switch SW74. One of the otherterminals of the switch SW70 is connected to an application terminal ofa pulse voltage Vpp and the other one of the other terminals of theswitch SW70 is connected to a low voltage supply terminal Vss. Thereference voltage generation circuit RC7 is configured to be able toapply either one of the pulse voltage Vpp and the low voltage Vss to thecontrol gate CG7 of the nonvolatile storage element M72 by switching theswitch SW70 as appropriate when the switch SW74 is in a connection state(short-circuit state).

As illustrated in FIG. 29, the reference voltage generation circuit RC7switches the switches SW70 to SW79 to the following states whenoutputting the reference voltage Vref from the voltage output terminalOUT.

Switch SW70: Arbitrary (low voltage Vss side in FIG. 29)

Switch SW71: High voltage supply terminal Vdd side

Switch SW72: Low voltage supply terminal Vss side

Switch SW73, SW74: Open state (open-circuit state)

Switches SW75, SW76, SW77, SW78: Connection state (short-circuit state)

Switch SW79: Arbitrary (low-voltage Vss side in FIG. 29)

In the reference voltage generation circuit RC7, a reference voltageVref is generated by bringing the switches SW70 to SW79 into theswitched state illustrated in FIG. 29 when the nonvolatile storageelement M71 is in a depression state and the nonvolatile storage elementM72 is in an enhancement state. More specifically, the reference voltagegeneration circuit RC7 is provided with a switch portion including theswitches SW70 to SW79 setting the potential of each terminal of thenonvolatile storage elements M71 and M72 to a desired potential.

As illustrated in FIG. 30, the reference voltage generation circuit RCswitches the switches SW70 to SW79 to the following states in rewritingfor bringing the nonvolatile storage element M71 into a depressionstate. Herein, a case where the threshold voltage before the adjustmenton the nonvolatile storage element M71 side is higher than the thresholdvoltage after the adjustment is taken as an example.

Switch SW70: Arbitrary (low voltage supply terminal Vss side in FIG. 30)

Switch SW71: Pulse voltage Vpp side

Switch SW72: Low voltage supply terminal Vss side switch

SW73: Connection state (short-circuit state)

Switch SW74: Open state (open-circuit state)

Switches SW75, SW76, SW77, SW78: Open-circuit state

Switch SW79: Low voltage supply terminal Vss side

Therefore, the pulse voltage Vpp is applied to the drain region D7 ofthe nonvolatile storage element M71 and the low voltage Vss is appliedto the control gate CG7, and therefore an electron is emitted to thedrain region D7 from the floating gate FG7 through the charge inlet 74.Thus, the threshold voltage of the nonvolatile storage element M71becomes low. On the contrary, when the low voltage Vss is applied to thedrain region D7 of the nonvolatile storage element M71 and the pulsevoltage Vpp is applied to the control gate CG7, an electron is injectedinto the floating gate FG7 from the drain region D7 through the chargeinlet 74. Thus, the threshold voltage of the nonvolatile storage elementM71 becomes high.

As illustrated in FIG. 31, the reference voltage generation circuit RC7switches the switches SW70 to SW79 to the following states in rewritingfor bringing the nonvolatile storage element M72 into an enhancementstate. Herein, a case where the threshold voltage before the adjustmenton the nonvolatile storage element M72 side is lower than the thresholdvoltage after the adjustment is taken as an example.

Switch SW70: Pulse voltage Vpp side

Switch SW71: High voltage supply terminal Vdd side

Switch SW72: Low voltage supply terminal Vss side

Switch SW73: Open state (open-circuit state)

Switch SW74: Connection state (short-circuit state)

Switches SW75, SW76, SW77, SW78: Open state (open-circuit state)

Switch SW79: Arbitrary (low voltage supply terminal Vss side in FIG. 31)

Therefore, the low voltage Vss is applied to the source region S7 of thenonvolatile storage element M72 and the pulse voltage Vpp is applied tothe control gate CG7, and therefore an electron is injected into thefloating gate FG7 from the source region S7 through the charge inlet 74.Thus, the threshold voltage of the nonvolatile storage element M72becomes high. On the contrary, when the pulse voltage Vpp is applied tothe source region S7 of the nonvolatile storage element M72 and the lowvoltage Vss is applied to the control gate CG7, an electron is emittedto the source region S7 from the floating gate FG7 through the chargeinlet 74. Thus, the threshold voltage of the nonvolatile storage elementM72 becomes low.

As illustrated in FIGS. 29 to 31, the reference voltage generationcircuit RC7 can rewrite the threshold voltages Vth of the specificnonvolatile storage elements M71 and M72 to desired values, and thengenerate a reference voltage Vref in a state finally illustrated in FIG.29 by switching the switches SW70 to SW79 as appropriate.

Thus, the drain regions D7 of the nonvolatile storage elements M71 andM72 receive a voltage when varying the threshold voltage to serve as acurrent path in the generation of the reference voltage Vref of thereference voltage generation circuit RC7. More specifically, in thenonvolatile storage element M71 and M72, the drain regions D7 functionas a writing voltage application region and a drain region of thedriving MOSFET.

Since the nonvolatile storage elements of the same type are used as theMOSFETs configuring the reference voltage generation circuits RC6 andRC7 in this embodiment, i.e., as the transistors, as with the referencevoltage generation circuits in the first embodiment described above, theconductance or the temperature characteristics can be made identical inthe two transistors, and thus the ideally translated characteristics ofthe two transistors can be obtained.

As described above, the nonvolatile storage element M7 according to thisembodiment is provided with the semiconductor substrate 9C, the floatinggate FG7 provided on the semiconductor substrate 9C, the control gateCG7 disposed above the floating gate FG7 to be insulated from thefloating gate FG7, the drain region D7 provided in the semiconductorsubstrate 9C and partially disposed below the floating gate FG7, and thetunnel insulating film 75 at least partially disposed between thefloating gate FG7 and the drain region D7 and having an area ratio tothe floating gate FG7 of 0.002 or more and 1 or less.

The nonvolatile storage element M7 having such a configuration cansuppress the first mode retention degradation and the second moderetention degradation.

The nonvolatile storage element M7 according to this embodiment isprovided with the floating gate FG7 having an area of 30 μm² or more.Thus, the nonvolatile storage element M7 according to this embodiment isusable as a MOSFET suitable for an analog circuit, such as a referencevoltage generating circuit. In the analog circuit provided with thenonvolatile storage element M7 according to this embodiment, acharacteristic fluctuation due to the retention degradation issuppressed and the influence of manufacturing variations or temperaturecharacteristics can be reduced.

The present invention is not limited to the above-described embodimentsand can be variously modified.

The tunnel insulating film may be formed by partially reducing the filmthickness of the gate insulating film. Also in this case, the first moderetention degradation and the second mode retention degradation can besuppressed due to the fact that the floating gate is formed to have anarea of 30 μm² or more and the tunnel insulating film is formed to havean area ratio to the floating gate of 0.002 or more 1 or less.

When the nonvolatile storage element is provided with the writingelement and the driving element and the tunnel insulating film is formedby reducing the film thickness of the gate insulating film, a recessedportion (level difference structure) is formed on the floating gate sidein the gate insulating film in the writing element. Therefore, thecontact surface with the floating gate FG is flatter in the gateinsulating film in the driving element than in the gate insulating filmin the writing element.

Although the writing elements in the first and second embodiments havethe gate insulating film and the tunnel insulating film having athickness smaller than that of the gate insulating film, the presentinvention is not limited thereto. For example, the writing elements inthe first and second embodiments may have a flat insulating film formedimmediately under the floating gate with such a film thickness that theinsulating film functions as a tunnel insulating film. In this case, theinsulating film functions as a tunnel insulating film and also functionsas a gate insulating film, and therefore the writing elements having theinsulating film can obtain the same effects as those of the writingelements in the first and second embodiments. When the area of theinsulating film and the area of the floating gate are the same, the arearatio of the tunnel insulating film to the floating gate is 1.

Although the nonvolatile storage element according to the thirdembodiment has the gate insulating film and the tunnel insulating filmhaving a thickness smaller than that of the gate insulating film, thepresent invention is not limited thereto. For example, the nonvolatilestorage element according to the third embodiment may have a flatinsulating film formed immediately under the floating gate with such afilm thickness that the insulating film functions as a tunnel insulatingfilm. In this case, the insulating film functions as a tunnel insulatingfilm and functions also as a gate insulating film, and therefore thenonvolatile storage element having the insulating film obtains the sameeffects as those of the nonvolatile storage element according to thethird embodiment. When the area of the insulating film and the area ofthe floating gate are the same, the area ratio of the tunnel insulatingfilm to the floating gate is 1.

The floating gate FG1 in the first embodiment may be isolated in thewriting element Mw1, the driving element Mv1, and the dummy element Mm1.When the floating gate is isolated, the floating gate of the writingelement Mw1, the floating gate of the driving element Mv1, and thefloating gate of the dummy element Mm1 need to be electrically connectedby a plug and a metal wiring line, for example, because the same voltageis applied thereto.

The control gate CG1 in the first embodiment may be isolated in thewriting element Mw1, the driving element Mv1, and the dummy element Mm1.When the control gate is isolated, the control gate of the writingelement Mw1, the control gate of the driving element Mv1, and thecontrol gate of the dummy element Mm1 need to be electrically connectedby a plug and a metal wiring line, for example, because the same voltageis applied thereto.

REFERENCE SIGNS LIST

-   9A, 9B, 9 c semiconductor substrate-   10A, 10B, 10 c P-well region-   10 z, 16 z oxide film-   11 a, 21 a diffusion layer-   11 m, 11 v, 71 d first drain layer-   12 a, 12 b, 12 md, 12 ms, 12 vd, 12 vm, 12 vs, 22 a, 22 d, 22 s, 72    d,-   72 LDD layer-   13 a, 13 b, 23 a contact layer-   13 md, 13 vd, 73 d second drain layer-   13 ms, 13 vs, 23 s, 73 s source layer-   14, 24, 74 charge inlet-   15, 25, 75 tunnel insulating film-   15 z opening portion-   16 m, 16 v, 16 w, 26 v, 26 w, 76 gate insulating film-   17, 27, 77 insulating film-   17 z ONO film-   18, 19, 28, 29, 78, 79 sidewall-   23 d drain layer-   41, 42, 43 element isolation region-   51 a, 51 b, 51 g, 51 md, 51 ms, 51 vd, 51 vs, 53 a, 53 d, 53 g, 53    s,-   55 d, 55 g, 55 s plug-   52 a, 52 b, 52 g, 52 md, 52 ms, 52 vd, 52 vs, 54 a, 54 d, 54 g, 54    s,-   56 d, 56 g, 56 s metal wiring line-   61, 62, 63 interlayer insulating film-   81 main circuit portion-   82 multistage inverter circuit-   83 switching circuit-   811 logic circuit portion-   812 analog circuit portion-   821 initial state inverter circuit-   821 a PMOSFET-   822 final stage inverter circuit-   CG1, CG2, CG7 control gate-   CGy oxide film-   CGz, FGz polysilicon film-   D1, D2, D7, Dm1, Dv1 drain region-   EC electronic circuit-   FA fluoride existing region-   FG1, FG2, FG7 floating gate-   IA impurity diffusion region-   IAa first impurity diffusion region-   IAb second impurity diffusion region-   M1, M2, M7, M11, M13, M21, M22, M31, M33, M51, M53, M71, M73    nonvolatile storage element-   Mm1, Mm11, Mm13, Mm31, Mm33, Mm51, Mm53 dummy element-   Mv1, Mv2, Mv11, Mv13, Mv21, Mv22, Mv31, Mv33, Mv51, Mv53 driving    element-   Mw1, Mw2, Mw11, Mw13, Mw21, Mw22, Mw31, Mw33, Mw51, Mw53 writing    element-   PA specific region-   RC2, RC3, RC6, RC7 reference voltage generation circuit-   RM11, RM15, RMc, RMf, RMfg resist mask-   S1, S2, S7, Sm1, Sv1 source region-   SW10 to SW15, S17, SW19, SW20 to SW25, S27, SW29, SW30 to SW35,-   S37, SW39, SW50 to SW55, S57, SW59, SW70 to 79 switch

What is claimed is:
 1. A nonvolatile storage element comprising: asemiconductor substrate; and a floating gate provided above thesemiconductor substrate, wherein the floating gate has an area of 30 μm²or more.
 2. A nonvolatile storage element comprising: a semiconductorsubstrate; and a floating gate provided above the semiconductorsubstrate, wherein a specific region of the floating gate has an area of17.5 μm² or more, and when a gate width of the specific region isdefined as W and a gate length of the specific region is defined as L, arelationship given by Expression 1 is satisfied: $\begin{matrix}{{9.28 \times 10^{- 5}} \geq \frac{W^{2.036}}{L^{2.215}}} & {{Expression}\mspace{14mu} 1}\end{matrix}$
 3. The nonvolatile storage element according to claim 2,wherein the specific region has an area of 30 μm² or more.
 4. Thenonvolatile storage element according to claim 1 further comprising: afirst region provided in the semiconductor substrate and partiallydisposed below the floating gate; and a tunnel insulating film at leastpartially disposed between the floating gate and the first region andhaving an area ratio to the floating gate of 0.002 or more and 1 orless.
 5. The nonvolatile storage element according to claim 2 furthercomprising: a first region provided in the semiconductor substrate andpartially disposed below the floating gate; and a tunnel insulating filmat least partially disposed between the floating gate and the firstregion and having an area ratio to the floating gate of 0.002 or moreand 1 or less.
 6. The nonvolatile storage element according to claim 3further comprising: a first region provided in the semiconductorsubstrate and partially disposed below the floating gate; and a tunnelinsulating film at least partially disposed between the floating gateand the first region and having an area ratio to the floating gate of0.002 or more and 1 or less.
 7. The nonvolatile storage elementaccording to claim 4, wherein an area of the tunnel insulating film is0.06 μm² or more and 54 μm² or less.
 8. The nonvolatile storage elementaccording to claim 5, wherein an area of the tunnel insulating film is0.06 μm² or more and 54 μm² or less.
 9. The nonvolatile storage elementaccording to claim 5, wherein a thickness of the tunnel insulating filmis 7 nm or more and 12 nm or less.
 10. The nonvolatile storage elementaccording to claim 5, wherein the tunnel insulating film containsfluorine.
 11. The nonvolatile storage element according to claim 5,wherein the first region functions as a writing voltage applicationregion and a drain region of a driving MOSFET.
 12. The nonvolatilestorage element according to claim 5 comprising: a gate insulating filmdisposed between the floating gate and the semiconductor substrate andhaving a film thickness larger than a film thickness of the tunnelinsulating film.
 13. The nonvolatile storage element according to claim5 further comprising: a second region provided in the semiconductorsubstrate and formed to be electrically isolated from the first region.14. The nonvolatile storage element according to claim 13, wherein thefirst region functions as a writing voltage application region, and thesecond region functions as a drain region of a driving MOSFET.
 15. Thenonvolatile storage element according to claim 8, wherein a thickness ofthe tunnel insulating film is 7 nm or more and 12 nm or less.
 16. Thenonvolatile storage element according to claim 8, wherein the tunnelinsulating film contains fluorine.
 17. The nonvolatile storage elementaccording to claim 8, wherein the first region functions as a writingvoltage application region and a drain region of a driving MOSFET. 18.The nonvolatile storage element according to claim 8 comprising: a gateinsulating film disposed between the floating gate and the semiconductorsubstrate and having a film thickness larger than a film thickness ofthe tunnel insulating film.
 19. The nonvolatile storage elementaccording to claim 8 further comprising: a second region provided in thesemiconductor substrate and formed to be electrically isolated from thefirst region.
 20. The nonvolatile storage element according to claim 6,wherein an area of the tunnel insulating film is 0.06 μm² or more and 54μm² or less.